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Articles

Design and Analysis of Memristor-based Combinational Circuits

References

  • S. Kang, and Y. Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, 3rd ed. New Delhi: Tata McGraw Hill, 2003, pp. 259–304.
  • R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits, International ed. New York: Mc Graw Hill, 1990, pp. 525–62.
  • K. Roy, and S. C. Prasad, Low Power CMOS VLSI Circuit Design. New York: Wiley, 2000.
  • H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-St. Circ., Vol. 19, pp. 468–73, Aug. 1984. doi: 10.1109/JSSC.1984.1052168
  • R. K. Watts, Ed., Submicron Integrated Circuits. New York: Wiley, 1989.
  • A. P. Chandrakashan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-St. Circ., Vol. 27, no. 4, pp. 473–84, Apr. 1992. doi: 10.1109/4.126534
  • N. Weste, and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective. Reading, MA: Addition-Wesley, 1986, pp. 15–17.
  • D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, Vol. 453, pp. 80–3, 2008. doi: 10.1038/nature06932
  • R. S. Williams, “How we found the missing memristor,” IEEE Spectrum, Vol. 45, pp. 28–35, 2008. doi: 10.1109/MSPEC.2008.4687366
  • D. B. Z. Biolek, and V. Biolkova, “SPICE model of memristor with nonlinear dopant drift,” Radio Eng. J., Vol. 18, pp. 210–14, 2009.
  • A. Shrivastava, M. Khalid, K. Singh, and J. Singh, “Improved dual sided doped memristor: modeling and applications,” J. Eng., Vol. 2014, pp. 219–26, 29th May 2014.
  • M. Khalid, and J. Singh, “Memristor-based unbalanced ternary logic gates,” Analog Integr. Circ. Signal Process., Vol. 87, pp. 399–406, 12th Apr. 2016. doi: 10.1007/s10470-016-0733-1
  • S. Kvatinsky, N. Wald, G. Satat, A. Kolodny, U. C. Weiser, and E. G. Friedman, “MRL – Memristor ratioed logic,” in IEEE, 13th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), Turin, Italy, 2012.
  • T. B. Singha, S. Konwar, S. Roy, and R. H. Vanlalchaka, “Power efficient priority encoder and decoder,” in International Conference on Computer Communication and Informatics (ICCCI – 2014), Jan. 3–5, 2014, Coimbatore, India.
  • Ata Elahi, and Trevor Arjeski, ARM Assembly Language with Hardware Experiments. Springer, 2014, pp. 32–3.
  • B. Dilli Kumar, and M. Bharathi, “Design of energy efficient binary to excess-3 converter using adiabatic techniques”, Int. J. Comput. Appl. Eng. Sci., Vol. III, no. I, pp. 14–19, Mar. 2013.
  • X. Yang, A. Adeyemo, A. Bala, and A. Jabir, “Novel techniques for memristive multifunction logic design,” Integr. VLSI J., VLSI1374. DOI: 10.1016/j.vlsi.2017.09.005.

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