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Articles

Threshold Voltage Modelling of Linearly Graded Binary Metal Alloy Gate Electrode with DP MOSFET

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References

  • M. Jagadesh Kumar and A. A. Orouji, “Two-dimensional Analytical Threshold Voltage Model of Nanoscale Fully Depleted SOI MOSFET With Electrically Induced S/D Extensions,” IEEE Trans. Electron Devices, Vol. 52, no. 7, July 2005. doi: 10.1109/TED.2002.1013294
  • E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Physical Model of the Junctionless UTB SOI-FET,” IEEE Trans. Electron Devices, Vol. 59, no. 4, April 2012. doi: 10.1109/TED.2011.2182353
  • W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, “Dual-material Gate (DMG) Field Effect Transistor,” IEEE Trans. Electron Devices, Vol. 46, no. 5, pp. 865–870, May 1999. doi: 10.1109/16.760391
  • M. Jurczak, T. Skotnicki, R. Gwoziecki, M. Paoli, B. Tormen, P. Ribot, D. Dutartre, S. Monfray, and J. Galvier, “Dielectric Pockets – A New Concept of the Junctions for Deca-Nanometric CMOS Devices,” IEEE Trans. Electron Devices, Vol. 48, no. 8, August 2001. doi: 10.1109/16.936706
  • C.-H. Shih, Yi-M. Chen, and C. Lien, “An Analytical Model of Short-Channel Effect for Metal–Oxide–Semiconductor Field Effect Transistor with Insulated Shallow Extension,” Japan. J. Appl. Phys., Vol. 43, part 1, no.12, pp. 7993–7996, December 2004. doi: 10.1143/JJAP.43.7993
  • B. Manna, S. Sarkhel, N. Islam, S. Sarkar, and S. K. Sarkar, “Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application,” IEEE Trans. Electron Devices, Vol. 59, no. 12, pp. 3280–3287, December 2012. doi: 10.1109/TED.2012.2220143
  • S. Deb, N. B. Singh, N. Islam, and S. K. Sarkar, “Work Function Engineering with Linearly Graded Binary Metal Alloy Gate Electrode for Short Channel SOI MOSFET,” IEEE Trans. Nanotechnol, Vol. 11, Issue 3, pp. 472–478, May 2012. doi: 10.1109/TNANO.2011.2177669
  • R. Ishii, K. Matsumura, A. Sakai, and T. Sakata, “Work Function of Binary Alloys,” Appl. Surf. Sci., Vol. 169–170, pp. 658–661, January 2001. doi: 10.1016/S0169-4332(00)00807-2
  • C. D. Gelatt and H. Ehrenreich, “Charge Transfer in Alloys: AgAu,” Phys. Rev. B, Vol. 10, no. 2, pp. 398–415, July 1974. doi: 10.1103/PhysRevB.10.398
  • Bing-Yue Tsui and Chih-Feng Huang, “Wide Range Work Function Modulation of Binary Alloys for MOSFET Application,” IEEE Electron Devices Lett., Vol. 24, no. 3, pp. 153–155, June 2003. doi: 10.1109/LED.2003.809528
  • A. Pan, R. Liu, M. Sun, and C.-Z. Ning, “Spatial Composition Grading of Quaternary ZnCdSSe Alloy Nanowires with Tunable Light Emission Between 350 and 710 nm on a Single Substrate,” ACS Nano, Vol. 4, no. 2, pp. 671–680, January 2010. doi: 10.1021/nn901699h
  • H. M. Christen, C. M. Rouleau, I. Ohkubo, H.Y. Zhai, H. N. Lee, S. Sathyamurthy, and D. H. Lowndes, “An Improved Continuous Compositional-spread Technique Based on Pulsed-laser Deposition and Applicable to Large Substrate Areas,” Rev. Sci. Instr., Vol. 74, pp. 4058–4062, June 2003. doi: 10.1063/1.1602962
  • D. Monroe and J. M. Hergenrother, “Evanescent-mode Analysis of Short-Channel Effects in Fully Depleted SOI and Related MOSFETs,” IEEE international SOI conference proceedings, pp. 157–158, August 2002.
  • Q. Chen, L. Wang, and J. D. Meindl, “Physics-based Device Models for Nanoscale Double-Gate MOSFETs,” Proceedings IEEE Int. conf. on integrated circuit design and technology, pp. 73–79, October 2004.
  • Te-K. Chiang, “Concise Analytical Threshold Voltage Model for Cylindrical Fully Depleted Surrounding-Gate Metal–Oxide Semiconductor Field Effect Transistors,” Japan. J. Appl. Phys., Vol. 44, part 1, no. 5A, pp. 2948–2952, May 2005. doi: 10.1143/JJAP.44.2948
  • R. Kaur, R. Chaujar, M. Saxena, and R. S. Gupta, “Two-dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension MOSFET,” Semicond. Sci. Technol, July 2007.
  • G. V. Reddy and M. J. Kumar, “A new Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET—Two-Dimensional Analytical Modeling and Simulation,” IEEE Trans. Electron Devices, Vol. 4, no. 2, March 2005.
  • K. Suzuki and T. Sugii, “Analytical Models for n+-p+ Double Gate SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 42, no. 11, November 1995.
  • ATLAS: 2-D Device Simulator, SILVACO International 2000.

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