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CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

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References

  • A. Jain, S. M. Alam, S. Pozder, and R. E. Jones, “Thermal-electrical co-optimization of floor planning of three-dimensional integrated circuits under manufacturing and physical design constraints,” IET Comput. Digital Tech., 2011, Vol. 5, no. 3, pp. 169–78, May 2011. doi: 10.1049/iet-cdt.2009.0107
  • T. Jhaveri, V. Rovner, L. Liebmann, L. Pileggi, A. J. Strojwas, and J. D. Hibbeler, “Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., Vol. 29, no. 4, pp. 509–27, Apr. 2010. doi: 10.1109/TCAD.2010.2042882
  • C.-J. Weng, “Feasibility study of process integration for high aspect ratio hard-mask scheme technologies of low-k/Cu interconnect fabrication,” J. Mater. Manuf. Process., Vol. 26, no. 9, pp. 1104–10, 2011. doi: 10.1080/10426914.2010.529592
  • A. K. Wong, “Some thoughts on the IC design-manufacture interface,” IEEE Des. Test Comput., Vol. 22, no. 3, pp. 206–13, Jun. 2005. doi: 10.1109/MDT.2005.70
  • A. Burmen, J. Puhan, and T. Tuma, “Robust design and optimization of operating amplifiers,” Industrial Technology, 2003 IEEE International Conference, Vol. 2, pp. 745–50, Dec. 2003.
  • A. K. Sinha, “Material interaction problems in semiconductor devices & integrated circuits,” IETE J. Res., Vol. 23, no. 9, pp. 575–6, 1977 (online publication Jul 2015). doi: 10.1080/03772063.1977.11451452
  • W. N. Borlea, and R. K. Bagaia, “On process induced defects in silicon wafer during device manufacture,” IETE J. Res., Vol. 19, no. 2, pp. 81–2, 1973 (online publication Aug 2015). doi: 10.1080/03772063.1973.11487118
  • A. Fontanelli, L. Arnone, R. Branca, and G. Mastrorocco, “Early addressing IC and package relationship allows an overall better quality of complex SOC,” IEEE Proceedings on Quality Electronic Design, ISQED 2000, pp. 121–6, March 2000.
  • J. Li, Q. Yan, and L. S. Melvin “Transferring optical proximity correction effects into a process model,” J. Vacuum Sci. Technol. B: Microelectron. Nanometer Struct., Vol. 26, no. 5, pp. 1808–12, Oct. 2008. doi: 10.1116/1.2981085
  • P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi, and X. Xu, “Wafer topography-aware optical proximity correction,” IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., Vol. 25, no. 12, pp. 2747–56, Dec. 2006. doi: 10.1109/TCAD.2006.882604
  • J. Li, L. Zhang, Q. Yan, L. S. Melvin, C. Lin, E. Su, and N. Tang, “Reducing the pattern redundancy in optical proximity correction modelling by analysing the pattern linearity,” J. Vacuum Sci. Technol. B: Microelectron. Nanometer Struct., Vol. 28, no. 6, pp. C6J19–24, Nov. 2010. doi: 10.1116/1.3511510
  • K. Lucas, C.-M. Yuan, R. Boone, K. Wimmer, K. Strozewski, and O. Toublan, “Logic design for printability using OPC methods,” IEEE Des. Test Comput., Vol. 23, no. 1, pp. 30–7, Jan./Feb. 2006 doi: 10.1109/MDT.2006.18
  • G. Klein, L. Kohler, J. Wiseman, B. Dunham, A.-T. Tran, S. Brown, M. Shingo, and I. Burki, “On the use of wafer positional and spatial pattern analysis to identify process marginality and to de-convolute counterintuitive experimental results,” International Symposium on Semiconductor Manufacturing, ISSM 2007. pp. 1–5, Oct. 2007.
  • H. Goel, and D. Dance, “Yield enhancement challenges for 90 nm and beyond,” Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI, 2003, pp. 262–5, March–April 2003
  • A. Vikram, V. Agarwal, D. Prakash, and A. Gangwar, “Multiple-patterning and systematic wafer inspection of VLSI devices for yield,” 2015 Annual IEEE India Conference (INDICON), pp. 1–6, 2015.
  • A. Vikram, V. Agarwal, and D. Prakash, “Multi-dimensional design layout analysis in ASIC manufacturing,” 2015 IEEE Students Conference on Engineering and Systems (SCES), pp. 1–5, 2015.
  • S. R. Nassif, “Technology modelling and characterization beyond the 45nm node,” Asia and South Pacific Design Automation Conference, ASPDAC 2008. pp. 219, Jan. 2008.
  • J. C. Le Denmat, V. Charbois, M. C. Luche, G. Kerrien, L. Couturier, L. Karsenti, and M. Geshel, “Tracking of design related defects hidden in the random defectively in a production environment,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference 2009, pp. 5–13, May 2009.
  • S. Mitra, K. Brelsford, Y. M. Kim, H.-H. K. Lee, and Y. Li, “Robust system design to overcome CMOS reliability challenges,” IEEE J. Emerg. Selected Topics Circuits Syst., Vol. 1, no. 1, pp. 30–41, Mar. 2011. doi: 10.1109/JETCAS.2011.2135630
  • C. Young, H. Liu, S. F. Tzou, D. Tsui, A. Tsai, and E. Chang, “Using design based binning to improve defect excursion control for 45nm production,” International Symposium on Semiconductor Manufacturing ISSM 2007, pp. 1–3, Oct. 2007.
  • M. Wu, W. Wang, L. Tian, C. Wu, and D. Fan, “Leakage in CMOS devices induced by pattern-dependent micro loading effect,” IEEE International Conference on Semiconductor Electronics (ICSE), 2012, pp. 440–3, Sept. 2012.
  • J. Luo, Q. Su, C. Chiang, and J. Kawa, “A layout dependent full-chip copper electroplating topography model,” IEEE/ACM International Conference on Computer-Aided Design, ICCAD-2005, pp. 133–40, May 2005.
  • J. H. Lee, S. J. Yu, and S. C. Park, “Design of intelligent data sampling methodology based on data mining,” IEEE Trans. Robotics Autom., Vol. 17, no. 5, pp. 637–49, Oct. 2001. doi: 10.1109/70.964664
  • J.-L. Baltzinger, S. Desmercieres, S. Lasserre, P. Champonnois, and M. Mercier, “E-beam inspection of dislocations: product monitoring and process change validation,” IEEE Conference and Workshop on Advanced Semiconductor Manufacturing, ASMC ‘04, pp. 359–66, May 2004.
  • H. W. Van Vliet, and K. Van Luttervelt, “Development and application of a mixed product/process-based DFM methodology,” Int. J. Comput. Integr. Manuf., Vol. 17, no. 3, pp. 224–34, 2004. doi: 10.1080/09511920310001600868
  • S. Vinodh and D. Rajanayagam, “CAD and DFM: enablers of sustainable product design,” Int. J. Sustain. Eng., Vol. 3, no. 4, pp. 292–8, Dec. 2010. doi: 10.1080/19397038.2010.501870
  • M. Valinataj, S. Mohammadi, and S. Safari, “Fault-aware and reconfigurable routing algorithms for networks-on-chip,” IETE J. Res.; J. Sci. Appl., Vol. 57, no. 3, pp. 215–23, 2011, Sep. 2014. doi: 10.4103/0377-2063.83642

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