References
- N. S. Naik and K. A. Gupta, “An efficient reconfigurable FIR digital filter using modified distribute arithmetic technique,” arXiv Preprint, arXiv:1704.08526, Apr. 2017.
- A. Rasekh and M. S. Bakhtiar, “Design of low-power low-area tunable active RC filters,” IEEE Trans. Circuits Syst. Express Briefs, Vol. 65, pp. 6–10, Jan. 2018. doi: 10.1109/TCSII.2017.2658635
- R. Thakur and K. Khare, “High-speed FPGA implementation of FIR filter for DSP applications,” Int. J. Model. Optim., Vol. 3, p. 92, Feb. 2013. doi: 10.7763/IJMO.2013.V3.242
- N. Bhagyalakshmi, K. R. Rekha, and K. R. Nataraj, “Design and implementation of DA-based reconfigurable FIR digital filter on FPGA,” in 2015 International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT), Dec. 2015, pp. 214–7. IEEE.
- S. J. Lee, J. W. Choi, S. W. Kim, and J. Park, “A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption,” IEEE Trans. VLSI Syst., Vol. 19, pp. 2221–8, Dec. 2011. doi: 10.1109/TVLSI.2010.2088142
- S. Karthick, S. Valarmathy, and C. Kamalanathan, “Design and performance analysis of a reconfigurable FIR filter,” Int. J. Innovations Eng. Technol. (IJIET), Vol. 8, no. 1, pp. 73–80, Jan. 2017.
- S. Y. Park and P. K. Meher, “Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter,” IEEE Trans. Circuits Syst. Express Briefs, Vol. 61, pp. 511–5, Jul. 2014. doi: 10.1109/TCSII.2014.2324418
- P. D. Shahare and S. S. Thorat, “A review: FPGA implementation of reconfigurable digital FIR filter,” Int. J. Sci. Res. (IJSR), Vol. 6, pp. 639–542, 2013.
- K. S. Reddy and H. N. Suresh, “A low power VLSI implementation of reconfigurable FIR filter using Carry Bypass adder,” Int. J. Intell. Eng. Sci., Vol. 11, pp. 225–36, 2018.
- A. Bonetti, A. Teman, P. Flatresse, and A. Burg, “Multipliers-driven perturbation of coefficients for low-power operation in reconfigurable FIR filters,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 64, pp. 2388–400, Sep. 2017. doi: 10.1109/TCSI.2017.2698138
- B. K. Mohanty, P. K. Meher, S. K. Singhal, and M. N. S. Swamy, “A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic,” Integr. VLSI J., Vol. 54, pp. 37–46, Jun. 2016. doi: 10.1016/j.vlsi.2016.01.006
- N. Sriram and J. Selvakumar, “A reconfigurable FIR filter architecture to trade off filter performance for dynamic power consumption,” Int. J. Adv. Comput. Theory Eng. (IJACTE), Vol. 2, pp. 2319–526, 2013.
- R. Jia, H. G. Yang, C. Y. Lin, R. Chen, X. G. Wang, and Z. H. Guo, “A computationally efficient reconfigurable FIR filter architecture based on coefficient occurrence probability,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., Vol. 35, pp. 1297–308, Aug. 2016. doi: 10.1109/TCAD.2015.2504922
- J. L. M. Iqbal and S. Varadarajan, “High performance reconfigurable FIR filter architecture using optimized multiplier,” Circuits Syst. Signal Process., Vol. 32, pp. 663–82, Apr. 2013. doi: 10.1007/s00034-012-9473-3
- D. Bhat, A. Kaur, and S. Singh, “Wireless sensor network specific low power FIR filter design and implementation on FPGA,” in 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), Mar. 2015, pp. 1534–6. IEEE.