https://orcid.org/0000-0001-9818-1775
References
- T. Chiarella, et al., “Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?,”in ESSDERC 2009 – Proceedings of the 39th European Solid-State Device Research Conference, 84–87, Sep 2009.
- Y. X. Liu, et al., “On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs,” Symposium on VLSI Technology, Honolulu, 2010, pp. 101–2.
- Mazurier Jerome, et al., “On the variability in planar FDSOI technology: From MOSFETs to SRAM cells,” IEEE Trans. Electron Devices, Vol. 58, no. 8, pp. 2326–2336, Aug. 2011.
- Samarth Agarwal, Terence B. Hook, Mohit Bajaj, Kevin McStay, Weike Wang, and Yanting Zhang, “Transistor matching and Fin angle variation in FinFET technology,” IEEE Trans. Electron Devices, Vol. 62, no. 4, Apr. 2015.
- Yuan Taur and Takh Ning, Fundamentals of Modern VLSI Devices. New York: Cambridge University Press, 1998, 2009.
- Nikolaos Fasarakis, et al., “Compact modeling of nanoscale trapezoidal FinFETs,” IEEE Trans. Electron Devices, Vol. 61, No. 2, pp. 324–32, Feb. 2014.
- [Online]. Available: http://www.eetimes.com/electronics-news/ 4373195/Intel-FinFETs-shape-revealed.
- D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda. “A fully depleted leanchannel transistor a novel vertical ultrathin SOI MOSFET,” IEEE Electron Device Lett., Vol. 11, no. 1, pp. 36–38, Jan. 1990. doi: https://doi.org/10.1109/55.46923
- M. Ko, C. Sohn, C. Baek, and Y. Jeong, “Study on a scaling length model for tapered tri-gate FinFET based on 3-D simulation and analytical analysis,” IEEE Trans. Electron Devices, Vol. 60, no. 9, Sep. 2013.
- S. Agarwal et al., “Ab initio study of metal grain orientation-dependent work function and its impact on FinFET variability,” IEEE Trans. Electron Devices, Vol. 60, no. 9, pp. 2728–33, Sep. 2013. doi: https://doi.org/10.1109/TED.2013.2272998
- Helen Margaret Lester Plants, Wallace Starr Venable, Introduction to Statics, Illustrated Edition. Morgantown, West Virginia: West Publishing Company, 1975, ISBN 0829900233, 9780829900231.
- Weina Peng, et al., “Probing the electronic structure at semiconductor surfaces using charge transport in nano membranes,” Nature Commun., Vol. 4, Art. ID 1339, 2013. doi:https://doi.org/10.1038/ncomms2350
- T. B. Hook, M. Vinet, R. Murphy, S. Ponoth, and L. Grenouillet, “Transistor matching and silicon thickness variation in ETSOI technology,” in Proc. IEEE IEDM, pp. 5–7, Dec. 2011.
- Yogesh Singh Chauhan, Darsen D. Lu, and Sriramkumar Vanugopalan, FinFET Modeling for IC Simulation and Design using the BSIM-CMG Standard. San Diego, CA: Elsevier Academic Press, 2015.
- J. E. Chung, M.-C. Jeng, J. E. Moon, P.-K. Ko, and C. Hu, “Performance and reliability design issues for deep-submicrometer MOSFETs,” IEEETrans. Electron Devices, Vol. 38, no. 3, pp. 545–54, Mar. 1991. doi: https://doi.org/10.1109/16.75165
- A. Donald. Neamen, Semiconductor Physics and Devices: Basic Principles, 3rd ed. New York: McGraw-Hill Education, 2003.
- Q. Zhang, C. Wang, H. Wang, C. Schnabel, D. G. Park, S. K. Springer, and E. Leobandung, “Experimental study of gate-first FinFET threshold voltage mismatch,” IEEE Trans. Electron Devices, Vol. 61, no. 2, pp. 643–6, Feb. 2014. doi: https://doi.org/10.1109/TED.2013.2295715
- T. Hook. FinFET on SOI: Potential Becomes Reality. [Online].Available:http://www.advancedsubstratenews.com/2013/11/finfet-onsoi-Potential-becomes-reality/.
- Hong-Wun Gao, Yeong-Her Wang, and Te-Kuang Chiang, “A quasi-3-D scaling length model for trapezoidal FinFET and its application to Subthreshold behavior analysis,” IEEE Trans. Nanotechnol., Vol. 16, no. 2, pp. 281–9, 2017. doi: https://doi.org/10.1109/TNANO.2017.2662018