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Articles

A High-Speed, Low-Power, and Area-Efficient FGMOS-Based Full Adder

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References

  • K. Bansal, and A. Dixit, “Advances in logic device scaling,” IETE Tech. Rev., Vol. 32, pp. 311–8, Apr. 2015. doi: 10.1080/02564602.2015.1023372
  • S. Shaik, K. S. R. Krishna, and R. Vaddi, “Nano-scale transistors with circuit interaction for designing energy-efficient and reliable adder cells at low VDD,” IETE Tech. Rev., Vol. 34, pp. 1–11, Jul. 2017.
  • S. Sharma, S. S. Rajput, and S. S. Jamuar, “Floating-gate MOS structures and applications,” IETE Tech. Rev., Vol. 25, pp. 338–45, 2008. doi: 10.4103/0256-4602.45426
  • R. Gupta, R. Gupta, and S. Sharma, “Design of high speed and low power 4-bit comparator using FGMOS,” AEU Int. J. Electron. Commun., Vol. 76, pp. 125–31, Apr. 2017. doi: 10.1016/j.aeue.2017.04.004
  • A. Kumar, “Split length FGMOS MOS cell: a new block for low voltage applications,” Analog. Integr. Circuits Signal. Process., Vol. 75, pp. 399–405, Jun. 2013. doi: 10.1007/s10470-012-0001-y
  • R. Gupta, R. Gupta, and S. Sharma, “High performance full subtractor using floating-gate MOSFET,” Microelectron. Eng., Vol. 162, pp. 75–8, Aug. 2016. doi: 10.1016/j.mee.2016.05.011
  • V. Foroutan, M. R. Taheri, K. Navi, and A. A. Mazreah, “Design of two low-power full adder cells using GDI structure and hybrid CMOS logic style,” Integr. VLSI J., Vol. 47, pp. 48–61, Jan. 2014. doi: 10.1016/j.vlsi.2013.05.001
  • A. Morgenshtein, A. Fish, and I. A. Wanger, “Gate-diffusion input (GDI) – a power efficient method for digital combinational circuits,” IEEE Trans. Very Large Scale Integration (VLSI), Vol. 10, pp. 566–81, Oct. 2002. doi: 10.1109/TVLSI.2002.801578
  • R. Uma, and P. Dhavachelvan, “Modified gate diffusion input technique: a new technique for enhancing performance in full adder circuits,” Proc. Technol., Vol. 6, pp. 74–81, 2012. doi: 10.1016/j.protcy.2012.10.010
  • A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, and A. Fish, “Full-swing gate diffusion input logic-case-study of low-power CLA adder design,” Integr. VLSI J., Vol. 47, pp. 62–70, Jan. 2014. doi: 10.1016/j.vlsi.2013.04.002
  • M. Shoba, and R. Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Eng. Sci. Technol.: Int. J., Vol. 19, pp. 485–96, Mar. 2016.
  • K. J. Singh, T. Sharan, and H. Tarunkumar, “High speed and low power basic digital logic gates, half-adder, and full-adder using modified gate diffusion input technology,” J. VLSI Des. Tools Technol., Vol. 8, pp. 34–42, Apr. 2018.
  • C. K. Tung, S. H. Shieh, and C. H. Cheng, “Low-power high speed full adder for portable electronic applications,” Electron. Lett., Vol. 49, pp. 1063–4, Aug. 2013. doi: 10.1049/el.2013.0893
  • K. Navi, M. H. Moaiyeri, R. F. Mirzaee, O. Hashemipour, and B. M. Nezhad, “Two new low-power full adders based on majority-not gates,” Microelectron. J., Vol. 40, pp. 126–30, Jan. 2009. doi: 10.1016/j.mejo.2008.08.020

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