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IETE Journal of Research Volume 69, 2023 - Issue 2
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Articles

Design and Simulation of Reliable Low Power CMOS Logic Gates

Vijay Kumar SharmaSchool of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra182 320, IndiaCorrespondence[email protected]
ORCID Iconhttps://orcid.org/0000-0001-9620-9404View further author information
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Pages 1022-1032 | Published online: 03 Dec 2020

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