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Articles

Utilizing Sneak Paths for Memristor Test Time Improvement

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References

  • L. Chua, “Memristor – The missing circuit element,” IEEE Trans. Circuit Theory, Vol. 18, no. 5, pp. 507–519, September 1971.
  • R. S. Williams, “How we found the missing memristor,” IEEE Spectr., Vol. 45, no. 12, pp. 28–35, Dec. 2008.
  • M. Chen, M. Sun, H. Bao, Y. Hu, and B. Bao, “Flux–charge analysis of two-memristor-based Chua’s circuit: Dimensionality decreasing model for detecting extreme multistability,” IEEE Trans. Ind. Electron., Vol. 67, no. 3, pp. 2197–2206, March 2020.
  • B. Bao, T. Jiang, G. Wang, P. Jin, H. Bao, and M. Chen, “Two-memristor-based Chuas hyperchaotic circuit with plane equilibrium and its extreme multistability,” Nonlinear Dyn., Vol. 89, no. 2, pp. 1157–1171, 2017.
  • R. Joshi, and J. M. Acken, “Sneak path characterization in memristor circuits,” J. Electron., pp.1–18, 2020.
  • M. Nourazar, V. Rashtchi, A. Azarpeyvand, and F. Merrikh-Bayat, “Code acceleration using memristor-based approximate matrix Multiplier: application to convolutional neural networks,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 26, no. 12, pp. 2684–2695, Dec. 2018.
  • M. Teimoori, A. Amirsoleimani, A. Ahmadi, and M. Ahmadi, “A 2M1M crossbar architecture: memory,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 26, no. 12, pp. 2608–2618, Dec. 2018.
  • A. Grossi, “Experimental investigation of 4-kb RRAM arrays programming conditions suitable for TCAM,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 26, no. 12, pp. 2599–2607, Dec. 2018.
  • M. T. Arafin, and G. Qu, “Memristors for secret sharing-based lightweight authentication,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 26, no. 12, pp. 2671–2683, Dec. 2018.
  • D. Chakraborty, and S. K. Jha. “Automated synthesis of compact crossbars for sneak-path based in-memory computing,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, 2017, pp. 770-77.
  • A. Mazady, M. T. Rahman, D. Forte, and M. Anwar, “Memristor PUF – a security primitive: theory and experiment,” IEEE J. Emerg. Selected Topics Circ. Syst., Vol. 5, no. 2, pp. 222–229, June 2015.
  • G. S. Rose, N. McDonald, L. Yan, B. Wysocki, and K. Xu. “Foundations of memristor based PUF architectures,” in 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Brooklyn, NY, 2013, pp. 52–57.
  • G. S. Rose, and C. A. Meade. “Performance analysis of a memristive crossbar PUF design,” in 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 2015, pp. 1–6.
  • Á Rak, and G. Cserey, “Macromodeling of the memristor in SPICE,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., Vol. 29, no. 4, pp. 632–636, April 2010.
  • F. García-Redondo, R. P. Gowers, A. Crespo-Yepes, M. López-Vallejo, and L. Jiang, “SPICE compact modeling of bipolar/unipolar memristor switching governed by electrical thresholds,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 63, no. 8, pp. 1255–1264, Aug. 2016.
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “TEAM: ThrEshold adaptive memristor model,” IEEE Trans. Circuits Syst. I Reg. Papers, Vol. 60, no. 1, pp. 211–221, Jan. 2013.
  • S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, “VTEAM: a general model for voltage-controlled memristors,” IEEE Trans. Circuits Syst. Express Briefs, Vol. 62, no. 8, pp. 786–790, Aug. 2015.
  • M. A. Zidan, and K. N. Salama, “Memristor based memory: the sneak paths problem and solutions,” Microelectr. J., Vol. 44, no. 2, pp. 176–183, Feb. 2013.
  • Y. Chen, and J. Li. “Fault modeling and testing of 1T1R memristor memories,” in 2015 IEEE 33rd VLSI Test Symposium (VTS), Napa, CA, 2015, pp. 1–6.
  • L. Sun, N. Zheng, T. Zhang, and P. Mazumder, “Fault modeling and parallel testing for 1T1M memory array,” IEEE Trans. Nanotechnol., Vol. 17, no. 3, pp. 437–451, May 2018.
  • Y. Luo, X. Cui, M. Luo, and Q. Lin. “A high fault coverage march test for 1T1R memristor array,” in 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, 2017, pp. 1–2.
  • S. N. Mozaffari, S. Tragoudas, and T. Haniotakis, “More efficient testing of metal-oxide memristor–based memory,” IEEE Trans. Comput. Aided Des. Integr. Circ. Syst., Vol. 36, no. 6, pp. 1018–1029, June 2017.
  • Q. Zhang, X. Cui, X. Xu, X. Wang, Z. Ma, and S. Zhou. “Sneak-path based test for 3D stacked one-transistor-N-RRAM array,” in 2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, 2016, pp. 226–229.
  • S. Kannan, J. Rajendran, R. Karri, and O. Sinanoglu. “Sneak-path Testing of Memristor-based Memories,” in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, Pune, 2013, pp. 386–391.
  • T. Li, X. Bi, N. Jing, X. Liang, and L. Jiang. “Sneak-path based test and diagnosis for 1R RRAM crossbar using voltage bias technique,” in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2017, pp. 1–6.
  • S. Kannan, N. Karimi, R. Karri, and O. Sinanoglu, “Modeling, detection, and diagnosis of faults in multilevel memristor memories,” IEEE Trans. Comput. Aided Des. Integr. Circ. Syst., Vol. 34, no. 5, pp. 822–834, May 2015.
  • Y. Li, J. Li, C. Hsu, and C. Sun. “Diagnosis of Resistive Nonvolatile-8T SRAMs,” in 2018 International SoC Design Conference (ISOCC), Daegu, Korea (South), 2018, pp. 23–24.
  • S. Kannan, R. Karri, and O. Sinanoglu. “Sneak path testing and fault modeling for multilevel memristor-based memories,” in 2013 IEEE 31st International Conference on Computer Design (ICCD), Asheville, NC, 2013, pp. 215–220.
  • S. Kannan, J. Rajendran, R. Karri, and O. Sinanoglu, “Sneak-path testing of crossbar-based nonvolatile random access memories,” IEEE Trans. Nanotechnol., Vol. 12, no. 3, pp. 413–426, May 2013.
  • S. Hamdioui, H. Aziza, and G. C. Sirakoulis. “Memristor based memories: Technology, design and test,” in 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Santorini, 2014, pp. 1–7.

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