Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material

References

• ITRS version 2.0, Available:http://www.semiconductors.org/main/2015-international-technology-roadmap-for-semiconductors-itrs/, 2015.
   Google Scholar
• J. P. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Springer, 2008.
   Google Scholar
• T. Al-Ameri, Y. Wang, V. P. Georgiev, F. Adamu-Lema, X. Wang, and A. Asenov, “Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors,” in IEEE NMDC, 2015, pp. 1-5.
   Google Scholar
• D. Nagy, G. Indalecio, A. J. García-Loureiro, M. A. Elmessary, K. Kalna, and N. Seoane, “FinFET versus gate-all-around nanowire FET: performance, scaling, and variability,” IEEE J. Electron Devices Soc., Vol. 6, pp. 332–340, Feb. 2018. doi:10.1109/JEDS.2018.2804383
   Web of Science ®Google Scholar
• S. Y. Lee, S. M. Kim, E. J. Yoon, C. W. Oh, I. Chung, D. Park, and K. Kim, “A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics,” IEEE Trans. Nanotechnol., Vol. 2, no. 7, pp. 253–257, Dec. 2003.
   Google Scholar
• S. Y. Lee, S. M. Kim, E. J. Yoon, C. W. Oh, I. Chung, D. Park, and K. Kim, “Three-dimensional MBCFET as an ultimate transistor,” IEEE Electron Device Lett., Vol. 25, no. 4, pp. 217–219, Mar. 2004. doi:10.1109/LED.2004.825199
   Web of Science ®Google Scholar
• S. Y. Lee, et al., Three-dimensional multi-bridge-channel MOSFET (MBCFET) fabricated on bulk Si-substrate,” in 62nd DRC Conf. Digest, 2004, pp. 119-120.
   Google Scholar
• E. J. Yoon, et al., “Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application,” in IEDM Technical Digest, 627–630, 2004.
   Google Scholar
• K. W. Ang, et al., “Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions” in IEDM Technical Digest, 2004, pp. 1069-1071.
   Google Scholar
• Y. Liu, et al., “Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy,” in IEEE Symp. VLSI Technology, 2007, pp. 44-45.
   Google Scholar
• Z. Ren, et al., “On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs,” in Symp. VLSI Technology, 2008, pp. 172-173.
   Google Scholar
• V. V. Kozlovski, A. E. Vasil’ev, V. V. Emtsev, G. A. Oganesyan, and A. A. Lebedev, “Dependence of the kinetics of radiation-induced defect formation on the energy absorbed by Si and SiC when exposed to fast charged particles,” J. Surf. Invest., Vol. 13, no. 6, pp. 1155–1159, Nov.2019. doi:10.1134/S1027451019060387
   Web of Science ®Google Scholar
• T. Ghani, et al., “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE IEDM, 2003, pp. 11-6.
   Google Scholar
• T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda, and S. Takagi, “High velocity electron injection MOSFETs for ballistic transistors using SiGe/strained-Si heterojunction source structures,” in Symp. VLSI Technology, 2004. pp. 202-203.
   Google Scholar
• A. A. Toropov, et al., “Tensile-strained GaAs quantum wells and quantum dots in a Ga As x Sb 1− x matrix,” Phys. Rev. B, Vol. 70, no. 20, pp. 205314, Nov.2014. doi:10.1103/PhysRevB.70.205314
   Google Scholar
• C. H. Ge, et al., “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEEE IEDM, 2003, pp. 3-7.
   Google Scholar
• S. A. Kumar, and J. C. Pravin, “Comparison and Simulation study of Cylindrical GAA NWMBCFET for sub 5 nm,” in Int. Semicond. Conf., 2019, pp. 89-92.
   Google Scholar
• F. Salimian, and D. Dideban, “Comparative study of nanoribbon field effect transistors based on silicene and graphene,” Mater. Sci. Semicond. Process., Vol. 93, pp. 92–98, Apr.2019. doi:10.1016/j.mssp.2018.12.032
   Web of Science ®Google Scholar
• F. Pan, et al., “Silicene nanomesh,” Sci. Rep., Vol. 5, pp. 9075, Mar.2015. doi:10.1038/srep09075
   PubMed Web of Science ®Google Scholar
• W. Liu, Z. F. Wang, Q. W. Shi, J. Yang, and F. Liu, “Band-gap scaling of graphene nanohole superlattices,” Phys. Rev. B, Vol. 80, no. 23, pp. 233405, Dec.2009. doi:10.1103/PhysRevB.80.233405
   Web of Science ®Google Scholar
• A. D. Franklin, et al., “Sub-10 nm carbon nanotube transistor,” Nano Lett., Vol. 12, no. 2, pp. 758–762, Feb.2012. doi:10.1021/nl203701g
   PubMed Web of Science ®Google Scholar
• A. Nourbakhsh, et al., “Mos2 field-effect transistor with sub-10 nm channel length,” Nano Lett., Vol. 16, no. 12, pp. 7798–7806, Dec.2016. doi:10.1021/acs.nanolett.6b03999
   PubMed Web of Science ®Google Scholar
• K. Nayak, et al., “CMOS logic device and circuit performance of Si gate all around nanowire MOSFET,” IEEE Trans. Electron Devices, Vol. 61, no. 9, pp. 3066–3074, Jul.2014. doi:10.1109/TED.2014.2335192
   Web of Science ®Google Scholar
• S. Bangsaruntip, et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” in IEEE IEDM, 2009, pp. 1-4.
   Google Scholar
• Sentaurus TCAD sdevice Manual, Available:http://www.sentaurus.dsod.pl/manuals/data/sdevice_ug.pdf.
   Google Scholar
• H. Harnal, A. Basu, S. K. Koul, R. K. Khatri, H. P. Vyas, and A. Kumar, “An improved model for GaAs MESFETs suitable for a wide bias range,” IEEE Microwave Wireless Compon. Lett., Vol. 17, no. 1, pp. 52–54, Jan.2007. doi:10.1109/LMWC.2006.887260
   Web of Science ®Google Scholar
• S. Azizian, V. Aziz Aghchegala, S. Azizian, and M. Sefidgar Dilmaghani, “CMOS bulk-controlled fully programmable neuron for artificial neural networks,” IETE J. Res., Vol. 65, no. 3, pp. 320–328, May 2019. doi:10.1080/03772063.2018.1431570
   Web of Science ®Google Scholar
• L. Liu, Y. Pang, W. Yuan, and J. Mu, “A self-powered piezoelectric energy harvesting interface with wide input range in 65 nm CMOS process,” IETE J. Res., Vol. 64, no. 6, pp. 753–763, Nov.2018. doi:10.1080/03772063.2017.1375439
   Web of Science ®Google Scholar