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Articles

Impact of High-K and Gate-to-Drain Spacing in InGaAs/InAs/InGaAs-based DG-MOS-HEMT for Low-leakage and High-frequency Applications

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REFERENCES

  • Q. Li, X. Zhou, C. W. Tang, and K. M. Lau, “High performance Inverted In0.7Ga0.3As MOSHEMTs on a GaAs substrate with regrown source/drain by MOCVD,” IEEE Electron Device Lett., Vol. 33, pp. 1246–1248, 2012.
  • B. R. Bennett, B. P. Tinkham, J. B. Boos, M. D. Lange, and R. Tsai, “Materials growth for InAs high electron mobility transistors and circuits,” J. Vac. Sci. Technol. B Microelectron. Nanom. Struct. Process. Meas. Phenom, Vol. 22, pp. 688–694, 2004.
  • J. Bergman, et al., “Low-voltage, high-performance InAs/AlSb HEMTs with power gain above 100 GHz at 100 mV drain bias,” Device Res. Conf. - Conf. Dig. DRC, Vol. 17, pp. 243–244, 2004.
  • R. Poornachandran, N. Mohankumar, R. S. Kumar, and G. Sujatha, “Sheet-carrier density and I-V analysis of In0.7Ga0.3As/InAs/In0.7Ga0.3As/InAs/In0.7Ga0.3As dual channel double gate HEMT for THz applications,” Int. J. Numer. Model, 2019.
  • M. R. Hasan, A. Motayed, M. S. Fahad, and M. V. Rao, “Fabrication and comparative study of DC and low frequency noise characterization of GaN/AlGaN based MOS-HEMT and HEMT,” J. Vac. Sci. Technol. B, Vol. 35, no. 52202, 2017.
  • D. Kim, and J. A. del Alamo, “30-nm inaspseudomorphic HEMTs on an InP substrate with a current-gain cutoff frequency of 628 GHz,” IEEE Electron Device Lett., Vol. 29, pp. 830–833, 2008.
  • J. Ajayan, T. D. Subash, and D. Kurian, “20 nm high performance novel MOSHEMT on InP substrate for future high speed low power applications,” Superlattices Microstruct., Vol. 109, pp. 183–193, 2017.
  • W. C. Kao, A. Ali, E. Hwang, S. Mookerjea, and S. Datta, “Effect of interface states on sub-threshold response of III–V MOSFETs, MOS HEMTs and tunnel FETs,” Solid. State. Electron., Vol. 54, pp. 1665–1668, 2010.
  • Q. Li, X. Zhou, C. W. Tang, and K. M. Lau, “Material and device characteristics of In0.53Ga0.47 AsMOSHEMTs grown on GaAs and Si substrates by MOCVD,” IEEE Trans. Electron Devices, Vol. 60, pp. 4112–4118, 2013.
  • E. Y. Chang, C. I. Kuo, H. T. Hsu, C. Y. Chiang, and Y. Miyamoto, “Inas thin-channel high-electron- mobility transistors with very high current-gain cutoff frequency for emerging submillimeter- wave applications,” Appl. Phys. Express, Vol. 6, pp. 4–7, 2013.
  • J. Ajayan, and D. Nirmal, “20 nm high performance enhancement mode InP HEMT with heavily doped S/D regions for future THz applications,” Superlattices Microstruct., Vol. 100, pp. 526–534, 2016.
  • D. Kim, and J. A. Alamo, “Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications,” IEEE Trans. Electron Devices, Vol. 55, pp. 2546–2553, 2008.
  • R. Poornachandran, N. Mohankumar, R. Saravanakumar, and G. Sujatha, “Analysis of microwave noise in an enhancement-mode dual-quantum-well InAs HEMT,” J. Comput. Electron., 1–11, 2019.
  • M. J. Rodwell, et al., “Record-Performance In(Ga)As MOSFETS targeting ITRS high-Performance and low-power logic,” ECS Trans., Vol. 66, no. 4, pp. 135, 2015.
  • C. Zhang, and X. Li, “III–V nanowire transistors for low-power logic applications: A review and outlook,” IEEE Trans. Electron Devices, Vol. 63, no. 1, pp. 223–234, 2016.
  • G. Dewey, et al., “III-V field effect transistors for future ultra-low power applications,” in 2012 IEEE Symposium on VLSI Technology (VLSIT), 2012.
  • M. J. W. Rodwell, et al., “Nanometer InP electron devices for VLSI and THz applications,” in Proc. 72ndAnnu. Device Res. Conf. (DRC), June, 2014, pp. 215–216.
  • G. Doornbos, and M. Passlack, “Benchmarking of III–V n-MOSFET maturity and feasibility for future CMOS,” IEEE Electron Device Lett., Vol. 31, no. 10, pp. 1110–1112, 2010.
  • X. Mei, et al., “First demonstration of amplification at 1 THz using 25-nm InP high electron mobility transistor process,” in IEEE Electron Device Lett., Vol. 36, no. 4, pp. 327–329, April, 2015
  • M. Daoudi, I. Dhifallah, A. Ouerghi, and R. Chtourou, “Si-delta doping and spacer thickness effects on the electronic properties in Si-delta-doped AlGaAs/GaAs HEMT structures,” Superlattices Microstruct., Vol. 51, no. 4, pp. 497–505, 2012. ISSN 0749-6036.
  • J. S. Flynn, et al., “Delta doped AlGaN and AlGaN/GaN HEMTs: Pathway to improved performance?,” Phys. Status Solidi, 2327–2330, 2003.
  • R. Saravana Kumar, A. Mohanbabu, N. Mohankumar, and D. Godwin Raj, “In0.7Ga0.3As/InAs /In0.7Ga0.3As composite-channel double-gate (DG)-HEMT devices for high-frequency applications,” J. Comput. Electron., Vol. 16, pp. 732–740, 2017.
  • M. Verma, and A. Nandi, “DC analysis of GaN-capped AlGaN/GaN HEMT for different gate-drain spacing,” in 2018 2nd Int. Conf. Inven. Syst. Control, 2018, pp. 1337–1340.
  • M. Rzin, et al., “Impact of gate–drain spacing on low-frequency noise performance of in situ SiNPassivatedInAlGaN/GaN MIS-HEMTs,” IEEE Trans. Electron Devices, Vol. 64, pp. 2820–2825, 2017.
  • TCAD Sentaurus. Sdevice user guide, ver.G-2016, Synopsys.
  • L.-F. Wu, Y.-M. Zhang, H.-L. Lv, and Y.-M. Zhang, “Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics,” Chin. Phys. B, Vol. 25, no. 10, pp. 108101-1–108101-5, 2016.
  • X. Zhou, C. Tang, Q. Li, and K. M. Lau, “In0.53Ga0.47As MOS-HEMTs on GaAs and Si substrates grown by MOCVD,” Phys. Status Solidi A, 1–4, 2012.
  • J.-W. Lee, V. Kumar, and I. Adesida, “High-Power-Density 0.25 µm gate-length AlGaN/GaN high-electron-mobility transistors on semi-insulating 6H–SiC substrates,” Jpn. J. Appl. Phys, Vol. 45, pp. 13–17, 2006.
  • Y. Yue, Y. Hao, J. Zhang, J. Ni, W. Mao, Q. Feng, and L. Liu, “AlGaN/GaN MOS-HEMT With HfO2 dielectric and Al2O3 interfacial passivation layer grown by atomic layer deposition,” IEEE Electron Device Lett., Vol. 29, pp. 838–840, 2008.
  • A. D. Carter, et al., “60 run gate length Al203/In0.53Ga0.47As gate-first MOSFETs using InAs raised source-drain regrowth,” in 69th Device Research Conference, Santa Barbara, CA, USA, Sep. 2011.
  • M. Egard, L. Ohlsson, B. M. Borg, F. Lennck, R. Wallenberg, L.-E. Wernersson, and E. Lind, “High Transconductance self-aligned gate-last surface channel In0.53Ga0.47As MOSFET,” in 2011 International Electron Devices Meeting, Washington, DC, USA, Jan. 2012.
  • D.-H. Kim, T.-W. Kim, M. Urteaga, and B. Brar, “Lg = 150 nm recessed quantum-well In0.7Ga0.3As MOS-HEMTs with Al2O3/In0.52Al0.48As composite insulator,” Electron. Lett., Vol. 48, no. 22, pp. 1430–1432, Oct, 2012.
  • T.-W. Kim, J. S. Kim, D.-K. Kim, S. H. Shin, W.-S. Park, S. Banerjee, and D.-H. Kim, “High-frequency characteristics of Lg = 60 nm InGaAs MOS high-electron-mobility transistor (MOS-HEMT) with Al2O3 gate insulator,” Electron. Lett., Vol. 52, no. 10, pp. 870–872, May 2016.
  • Q. Li, X. Zhou, C. Tang, and K. M. Lau, “High-performance inverted In0.53Ga0.47As MOSHEMTs on a GaAs substrate with regrown source/drain by MOCVD,” IEEE Electron Device Lett., Vol. 33, no. 9, Sep. 2012.
  • J. Lin, X. Cai, Y. Wu, D. A. Antoniadis, and J. A. del Alamo, “Record maximum transconductance of 3.45 mS/µm for III-V FETs,” IEEE Electron Device Lett., Vol. 37, no. 4, pp. 381–384, Apr. 2016.
  • N. Mohankumar, B. Syamal, and C. K. Sarkar, “Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs,” in IEEE Trans. Electron Devices, Vol. 57, no. 4, pp. 820–826, 2010.
  • D.-H. Kim, and J. A. del Alamo, “30 nm E-mode InAs PHEMTs for THz and future logic applications,” in 2008 IEEE International Electron Devices Meeting, Dec. 15–17, 2008.
  • T. Takahashi, et al., “Enhancement of fmax to 910 GHz by adopting asymmetric gate recess and double-side-doped structure in 75-nm-gate InAlAs/InGaAs HEMTs,” IEEE Trans. Electron Devices, Vol. 64, pp. 89–95, 2017.
  • D. C. Ruiz, T. Saranovac, D. Han, A. Hambitzer, A. M. Arabhavi, O. Ostinelli, and C. R. Bolognesi, “InAs channel inset effects on the DC, RF, and noise properties of InP pHEMTs,” IEEE Trans. Electron Devices, Vol. 66, no. 11, Nov. 2019.
  • M. A. UttamSingisetti, et al., “In0.53Ga0.47As channel MOSFETs with self-aligned InAs source/drain formed by MEE regrowth,” IEEE Electron Device Lett., Vol. 30, no. 11, Nov. 2009.
  • P. Chang, et al., “Self-aligned inversion-channel In0.53Ga0.47As metal–oxide–semiconductor field-effect transistors with in-situ deposited Al2O3/Y2O3 as gate dielectrics,” Appl. Phys. Express, Vol. 4, pp. 114202, 2011.

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