Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations

References

• N. Jagadeesh kumar, and D. Meganathan, “A systematic design of novel energy efficient 64-bit parallel-prefix adder,” Int. J. Electron., Vol. 108, no. 21, pp. 1821–1842, Jan 2021. doi:10.1080/00207217.2020.1870746.
   Google Scholar
• A. N. Yakunin, et al., “Improving the operating efficiency of a multibit binary parallel-prefix adder,” Russ. Microlectron., Vol. 50, no. 7, pp. 491–498, Mar 2021. doi:10.1134/s106373972107012x.
   Google Scholar
• S. Sam, et al., “Design techniques in carry select adder using parallel prefix adder for improved switching energy,” Przegląd Elektrotechniczny, Vol. 1, no. 5, pp. 152–155, May 2021. ISSN 0033-2097.
   Google Scholar
• K. Srivalli, G. H. Medha, K. P. Meghna, A. Mohan Kumar, and D. Halliyavar, “Comparison and analysis of performance parameters of basic adders with sparse adder,” Int. J. Eng. Appl. Sci. Technol., Vol. 6, no. 3, pp. 145–150, Jul 2022.
   Google Scholar
• G. Thakur, H. Sohal, and S. Jain, “A novel ASIC-based variable latency speculative parallel prefix adder for image processing application,” Circuits Syst. Signal Process, Vol. 40, pp. 5682–5704, May 2021. doi:10.1007/s00034-21-01741-6.
   Web of Science ®Google Scholar
• S. Elango, and P. Sampath, “Implementation of high performance hierarchy-based parallel signed multiplier for cryptosystem,” J. Circuits Syst. Comput., Vol. 29, no. 13, pp. 205–214, Mar. 2020. doi:10.1142/S021812662050214X.
   Web of Science ®Google Scholar
• V. Thamizharasan, and N. Kasthuri, “High-speed hybrid multiplier design using a hybrid adder with FPGA implementation,” IETE. J. Res., April 2021. doi:10.1080/03772063.2021.1912655.
   Web of Science ®Google Scholar
• K. Prasanthi, et al., “Comparative analysis of 16-bit parallel prefix adders,” J. Compos. Theory, Vol. 15, no. 4, pp. 71–75, Apr. 2021.
   Google Scholar
• P. Sireesha, et al., “Design and analysis of 32 bit high speed carry select adder,” J. Phys. Conf. Ser., Vol. 1916, pp. 012006, Vol:10, pp. 1742–1755, Mar. 2021. doi:10.1088/1742-6596/1916/1/012006
   Google Scholar
• T.-D. Ene, and J. E. Stine. “A comprehensive exploration of the parallel prefix adder tree space,” in IEEE 39th International Conference on Computer Design (ICCD), Vol. 1, no. 1, pp. 125−129, Jun 2021. doi: 10.1109/ICCD53106.2021.00030.
   Google Scholar
• P. Kumar, et al., “Design and implementation of array multiplier using compressor for low power,” Int. Conf. Adv. Technol. (ICONAT), Vol. 2405, no. 1, pp. 1–6, Feb 2022. doi:10.1109/ICONAT53423.2022.9725934.
   Google Scholar
• J. Reuben, et al., “Design of in-memory parallel-prefix adders,” J. Low Power Electron. Appl., Vol. 11, no. 45, Nov. 2021. doi:10.3390/jlpea11040045.
   Google Scholar
• H. Ghabeli, et al., “Variable latency carry speculative adders with input-based dynamic configuration,” Comput. Electr. Eng., Vol. 93, pp. 107–117, Jul 2021. ISSN 0045-7906. doi:10.1016/j.compeleceng.2021.107247.
   Web of Science ®Google Scholar
• P. Patali, and S. T. Kassim, “An efficient architecture for signed carry save multiplication,” IEEE Lett. Comput. Soc., Vol. 3, no. 1, pp. 9–12, Jun. 2020. doi:10.1109/LOCS.2020.2971443.
   Google Scholar
• V. Vijayakumar, K. T. Ilayarajaa, T. Ravi, and M. Sugade, “Analysis of high speed hybrid full adder,” Int. Conf. Artif. Intell. Smart Syst. (ICAIS), 1641–1645, Apr 2021. doi:10.1109/ICAIS50930.2021.9395998.
   Google Scholar
• A. Simson, and D. S. et al. “Design and implementation of high speed hybrid carry select adder,” in International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT),Vol. 1, pp. 1–6, Feb. 2021. doi:10.1109/ICAECT49130.2021.9392452.
   Google Scholar
• M. A. Akbar, B. Wang, and A. Bermak, “A high-speed parallel architecture for ripple carry adder with fault detection and localization,” Electronics, Vol. 10, no. 1791, pp. 1–10, Jul. 2021. doi:10.3390/electronics10151791.
   Google Scholar
• A. A. Del Barrio, R. Hermida, and S. Ogrenci-Memik, “A combined arithmetic-high-level synthesis solution to deploy partial carry-save radix-8 booth multipliers in Datapaths,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 66, no. 2, pp. 742–755, Feb. 2019. doi:10.1109/TCSI.2018.2866172.
   Web of Science ®Google Scholar
• M. Hasan, et al., “A high-speed and scalable XOR-XNOR-based hybrid full adder design,” Comput. Electr. Eng., Vol. 93, pp. Article 107200, July 2021. doi:10.1016/j.compeleceng.2021.107200.
   Web of Science ®Google Scholar
• S. Sarkar, S. Sarkar, and J. Mehedi, “Modified CSA-CIA for reducing propagation delay,” Int. Conf. Comput. Commun. Inf. (ICCCI), Vol. 5, pp. 1–5, Aug 2018. doi:10.1109/ICCCI.2018.8441482.
   Google Scholar
• S. Radhakrishnan, T. Nirmalraj, R. K. Karn, and S. K. Pandiyan, “Low latency power aware self checking based CSA for sequential multiplier,” IEEE Int. Conf. Power Control Signals Instrum. Eng. (ICPCSI), Vol. 1, pp. 1056–1059. doi:10.1109/ICPCSI.2017.8391872.
   Google Scholar
• B. Silveira, et al., “Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 64, no. 12, pp. 3126–3137, Dec. 2017. doi:10.1109/TCSI.2017.2728802.
   Web of Science ®Google Scholar
• M. S. Hossain, and F. Arifin, “Design and evaluation of a 32-bit carry select adder using 4-bit hybrid CLA adder,” AIUB J. Sci. Eng. (AJSE), Vol. 20, no. 2, pp. 1–7, May 2021. doi:10.53799/ajse.v20i2.119
   Google Scholar
• G. Thakur, H. Sohal, and S. Jain, “A novel parallel prefix adder for optimized Radix-2 FFT processor,” Multidimens. Syst. Signal Process., Vol. 32, no. 3, pp. 1041–1063, Jul. 2021. doi:10.1007/s11045-021-00772-1.
   Web of Science ®Google Scholar
• N. A. Gudala, T. Ytterdal, J. J. Lee, and M. Rizkalla, “Implementation of high speed and low power carry select adder with BEC,” IEEE Int. Midwest Symp. Circuits Syst. (MWSCAS), Vol. 1, pp. 377–381, Aug. 2021. doi:10.1109/MWSCAS47672.2021.9531750.
   Google Scholar
• A. S. Hameed, and M. J. Kathem, “Highspeed modified carry save adder using a structure of multiplexers,” Int. J. Electr. Comput. Eng., Vol. 11, no. 2, pp. 1591–1598, Apr. 2021, ISSN: 2088-8708. doi: 10.11591/ijece.v11i2.pp1591-1598.
   Google Scholar
• H. You, J. Yuan, W. Tang, and S. Qiao, “An energy and area efficient carry select adder with dual carry adder cell,” Electronics (Basel), Vol. 8, no. 10, pp. 1129–1139, Oct. 2019.
   Web of Science ®Google Scholar
• M. Bahadori, M. Kamal, A. Afzali-Kusha, and M. Pedram, “High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, no. 2, pp. 421–433, Feb. 2016. doi: 10.1109/TVLSI.2015.2405133.
   Web of Science ®Google Scholar
• N. V. V. K. Boppana, S. Ren, and H. Chen. “Low-power and high speed CPL-CSA adder,” in NAECON 2014 – IEEE National Aerospace and Electronics Conference, Vol. 1, pp. 346−350, Jun. 2014. doi: 10.1109/NAECON.2014.7045834.
   Google Scholar
• S. Daphni, et al., “Design and analysis of 32-bit parallel prefix adders for low power VLSI applications,” ASTES J., Vol. 4, no. 2, pp. 102–106, Mar. 2019. doi:10.25046/aj040213
   Google Scholar
• A. K. Panda, R. Palisetty, and K. C. Ray, “High-speed area-efficient VLSI architecture of three-operand binary adder,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 67, no. 11, pp. 3944–3953, Nov. 2020. doi:10.1109/TCSI.2020.3016275.
   Web of Science ®Google Scholar
• P. Pramod, and T. K. Shahana, “Delay and energy efficient modular hybrid adder for signal processor architectures,” IETE. J. Res., Jun 2019. ISSN: 0377-2063. doi: 10.1080/03772063.2019.1627917.
   Web of Science ®Google Scholar
• K. Papachatzopoulos, and V. Paliouras, “Low-power addition with borrow-save adders under threshold voltage variability,” IEEE Trans. Circuits Syst. Express Briefs, Vol. 65, no. 5, pp. 572–576, May 2018. doi:10.1109/TCSII.2018.2821905.
   Web of Science ®Google Scholar
• S. Sarabdeep, and K. M. Dilip, “Design of area and power efficient modified carry select adder,” Int. J. Comput. Appl., Vol. 33, no. 3, pp. 14–18, Nov. 2011.
   Google Scholar
• B. S. Kandula, P. V. Kalluru, and S. P. Inty, “Design of area efficient VLSI architecture for carry select adder using logic optimization technique,” Comput. Intell., Vol. 36, pp. 1–11, May 2020. doi:10.1111/coin.12221
   Google Scholar
• S. K. Singhal, B. K. Mohanty, S. K. Patel, and G. Saxena, “Efficient diminished-1 modulo (2n+12n+1) adder using parallel prefix adder,” J. Circuits Syst. Comput., Vol. 29, no. 12, pp. 202–212, May 2022.
   Web of Science ®Google Scholar
• S. A. Simon, and S. S. “Implementation of carry save adder using novel eighteen transistor hybrid full adder,” in International Conference on Power Electronics and Renewable Energy Applications (PEREA), pp. 1−4, Feb 2021. doi: 10.1109/PEREA51218.2020.9339799.
   Google Scholar
• P. K. and R, and K. Sharma, “An energy efficient logic approach to implement CMOS full adder,” J. Circuit Syst. Comp., Vol. 26, no. 5, pp. 1–20, May 2017.
   Web of Science ®Google Scholar
• C. L. Ayala, N. Takeuchi, Y. Yamanashi, T. Ortlepp, and N. Yoshikawa, “Majority-logic-optimized parallel prefix carry look-ahead adder families using adiabatic quantum-flux-parametron logic,” IEEE Trans. Appl. Supercond., Vol. 27, no. 4, pp. 1–7, June 2017. doi:10.1109/TASC.2016.2642041.
   Web of Science ®Google Scholar
• S. Das, and S. P. Khatri, “A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 16, no. 3, pp. 326–331, Mar. 2008. doi: 10.1109/TVLSI.2007.915507.
   Web of Science ®Google Scholar
• N. Drego, A. Chandrakasan, and D. Boning, “All-digital circuits for measurement of spatial variation in digital circuits,” IEEE J. Solid-State Circuits, Vol. 45, no. 3, pp. 640–651, Mar. 2010. doi: 10.1109/JSSC.2009.2039270.
   Web of Science ®Google Scholar
• T. Prasad, K. Sathyanarayanan, S. Tiwari, N. Goveas, and B. Deshpande. “t-CSA: A fast and flexible CSA implementation” in 8th International Conference on Communication Systems and Networks (COMSNETS), Vol. 1, pp. 1−6, May 2016. doi: 10.1109/COMSNETS.2016.7439937.
   Google Scholar
• U. S. Kumar, K. K. Salih, and K. Sajith, “Design and implementation of carry select adder without using multiplexer,” Proc. IEEE Int. Conf. Emerg. Technol. Trends Electron. Commun. Networking, Vol. A24, no. 7, pp. 529–551, Feb. 2013.
   Google Scholar
• R. Javali, et al., “Design of high speed carry save adder using carry look-ahead adder,” Proc. Int. Conf. Circuits Commun. Control Comput., Vol. 1, pp. 33–36, Mar. 2015.
   Google Scholar
• H. Parandeh-Afshar, A. K. Verma, P. Brisk, and P. Ienne, “Improving FPGA performance for carry-save arithmetic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 18, no. 4, pp. 578–590, Apr. 2010. doi: 10.1109/TVLSI.2009.2014380.
   Web of Science ®Google Scholar
• Y. S. Lin, and D. Radhakrishnan, “Delay efficient 32-Bit carry-skip adder,” VLSI Des., Vol. 3, no. 7, pp. 218–226, Article ID 218565, Apr. 2008.
   Google Scholar
• N. Burgess, et al., “Accelerated carry-skip adders with low hardware cost,” Proc. Conf. Signals Syst. Comput. Pac. Grove CA USA, Vol. 1, pp. 852–853, Aug. 2011.
   Google Scholar
• R. Zlatanovici, S. Kao, and B. Nikolic, “Energy-delay optimization of a 64-bitcarry – look ahead adders with a 420ps 90 um CMOS design example,” IEEE J. Solid-State Circuits, Vol. 44, no. 2, pp. 569–583, June 2009. doi:10.1109/JSSC.2008.2010795
   Web of Science ®Google Scholar
• N. Radha, M. Maheswari, and P. Muralikrishnan. “An efficient implementation of hybrid carry select adder using parallel prefix addition and binary to excess 1 conversion” in Proceedings of International Conference on Recent Trends in Computing, Communication & Networking Technologies (ICRTCCNT), Vol. 1, pp. 1−6, Aug 2019.
   Google Scholar
• R. Gupta, R. Gupta, and S. Sharma, “A high-speed, low-power, and area-efficient FGMOS-based full adder,” IETE. J. Res., 1–7, Dec. 2019. doi:10.1080/03772063.2019.1700833.
   Web of Science ®Google Scholar
• B. Parhami. Computer Arithmetic: Algorithms and Hardware Designs. 2nd edition. New York: Oxford University Press, 2010. ISBN 978-0-19-532848-6.
   Google Scholar