https://orcid.org/0000-0002-0180-7610
References
- G. Bourianoff, “The future of nanocomputing,” IEEE Comput., Vol. 38, no. 8, pp. 44–53, 2003.
- M. Kule, H. Rahaman, and B. B. Bhattacharya, “Reliable logic design with defective nano-crossbar architecture,” in IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2016, pp. 47–52.
- M. Kule, H. Rahaman, and B. B. Bhattacharya, “Function-Mapping on defective nano-crossbar with enhanced reliability,” J. Comput. Electron., Vol. 19, no. 2, pp. 555–64, 2020.
- Y. Yellambalase, and M. Choi, “Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects,” J. Syst. Archit., Vol. 54, pp. 729–41, 2008.
- M. Butts, S. C. Glodstein, and A. DeHon, “Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips,” ICCAD, 2002, pp. 443–40.
- M. Kule, H. Rahaman, and B. B. Bhattacharya, “On finding a defect-free component in nanoscale crossbar circuits,” ICECCS, Procedia Comput. Sci., Vol. 70, pp. 421–7, 2015.
- M. Kule, H. Rahaman, and B. B. Bhattacharya, “Maximal defect-free component in nanoscale crossbar circuits amidst stuck-open and stuck-closed faults,” J. Circuit Syst. Comput., Vol. 28, no. 11, pp. 1950180:1––1950180:22, 2019.
- T. Hogg, and G. Snider, “Defect-tolerant logic with nanoscale crossbar circuits,” J. Electron. Test., Theory Appl., Vol. 23, no. 2–3, pp. 117–29, 2007.
- A. DeHon, and M. J. Wilson, “Nanowire-Based Sublithographic Programmable Logic Arrays,” FPGA, 2004, pp. 123–32.
- H. Rahaman, and M. Kule. “Defect tolerant approaches for function mapping in nano-crossbar circuits,” IEEE International Conference on Research in Computational Intelligence and Communication Networks, 2018, pp. 48–53.
- M. Kule, A. Dutta, H. Rahaman, and B. B. Bhattacharya, “High-speed decoder design using memristor-based nano-crossbar architecture,” Sixth IEEE International Symposium on Embedded Computing and System Design (ISED), 2016, pp. 77–81.
- J. S. Yang, and R. Datta, “Efficient Function Mapping in Nanoscale Crossbar Architecture,” DFT’11, 2011, pp. 190–6.
- H. Naeimi, and A. DeHon, “A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design,” FPT, 2004, pp. 49–56.
- Y. Su, and W. Rao, “Defect-tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis,” DFT’09, 2009, pp. 322–30
- D. E. Goldberg. Genetic algorithms in search, optimization & machine learning. Reading, MA: Addison Wesley, 1989.
- P. Manna, D. K. Kole, H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Reversible logic circuit synthesis using genetic algorithm and particle swarm optimization,” IEEE International Symposium on Embedded Computing and System Design (ISED), 2012, pp. 246–50.