Full RLGC model extraction of Through Silicon Via (TSV) with charge distribution effects

References

• Garrou P, Bower C, Ramm P. Handbook of 3D integration. Weinheim: Wiley-VCH Verlag GmbH & Co. KGaA; 2008.10.1002/9783527623051
   Google Scholar
• Li E-P. Electrical modeling and design for 3D system integration. New York (NY): Wiley-IEEE Press; 2012.10.1002/9781118166727
   Google Scholar
• Ryu C, Park J, Pak JS, Lee K, Oh T, Kim J. Suppression of power/ground inductive impedance and simultaneous switching noise using Silicon Through-Via in a 3-D stacked chip package. IEEE Microw. Wireless Compon. Lett. 2007;17:855–857.10.1109/LMWC.2007.910485
   Web of Science ®Google Scholar
• Kim J, Lee W, Shim Y, Shim J, Jim K, Pak JS, Kim J. Chip-package-hierarchical power distribution network modeling and analysis based on a segmentation method. IEEE Trans. Adv. Packaging. 2010;33:647–659.
   Web of Science ®Google Scholar
• Cho J, Song E, Yoon K, Pak JS, Kim J. Modeling and analysis of a Through Silicon Via (TSV) noise coupling and suppression using a guard ring. IEEE Trans. Comp. Packag. Manuf. Technol. 2011;1:220–233.
   Web of Science ®Google Scholar
• Pak JS, Kim J, Cho J, Kim K, Song T, Ahn S, Lee J, Lee H, Park K, Kim J. PDN Impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip PDN models. IEEE Trans. Comp. Packag. Manuf. Technol. 2011;1:208–219.
   Web of Science ®Google Scholar
• Kim K, Hwang C, Koo K, Cho J, Kim H, Kim J, Lee J, Lee HD, Park KW, Park JS. Modeling and analysis of a power distribution network in TSV-Based 3-D Memory IC Including P/G TSVs, on-chip decoupling capacitors, and silicon substrate effects. IEEE Trans. Comp. Packag. Manuf. Technol. 2012;2:2057–2070.10.1109/TCPMT.2012.2214482
   Web of Science ®Google Scholar
• Kim J, Pak JS, Cho J, Kim J. High-frequency scalable electrical model and analysis of a Through Silicon Via (TSV). IEEE Trans. Comp. Packag. Manuf. Technol. 2011;1:181–195.
   Web of Science ®Google Scholar
• Xu Z, Lu J-Q. Through-strata-via (TSV) parasitics and wideband modeling for three-dimensional integration/packaging. IEEE Electron Device Lett. 2011;32:1278–1280.10.1109/LED.2011.2158511
   Web of Science ®Google Scholar
• Xie B, Swaminthan M. Electromagnetic modeling of non-uniform Through-Silicon Via(TSV) interconnections. In: 2012 IEEE 16th Workshop on Signal and Power Integrity(SPI); Sorrento; 2012. p. 43–46.
   Google Scholar
• Yao W, Pan S, Achkir B, Fan J, He L. Modeling and application of multi-port TSV networks in 3-D IC. IEEE Trans. Computer-Aided Design Integr. Circuits Syst. 2013;32:487–496.10.1109/TCAD.2012.2228740
   Web of Science ®Google Scholar
• Kandalaft N, Rashidzadeh R, Ahmadi M. Testing 3-D IC Through-Silicon-Vias (TSVs) by direct probing. IEEE Trans. Computer-Aided Design Integr. Circuits Syst. 2013;32:538–546.10.1109/TCAD.2012.2237226
   Web of Science ®Google Scholar
• Katti G, Stucchi M, De Meyer K, Dehaene W. Electrical modeling and characterization of Through Silicon Via for three-dimensional ICs. IEEE Trans. Electron Devices. 2010;57:256–262.10.1109/TED.2009.2034508
   Web of Science ®Google Scholar
• Xu C, Li H, Suaya R, Banerjee K. Compact AC modeling and performance analysis of Through-Silicon Vias in 3-D ICs. IEEE Tran. Electron Devices. 2010;57:3405–3417.10.1109/TED.2010.2076382
   Web of Science ®Google Scholar
• Bandyopadhyay T, Han KJ, Chung D, Chatterjee R, Swaminathan M, Tummala R. Rigorous electrical modeling of Through Silicon Vias (TSVs) with MOS capacitance effects. IEEE Trans. Comp. Packag. Manuf. Technol. 2011;1:893–903.10.1109/TCPMT.2011.2120607
   Web of Science ®Google Scholar
• Sze SM. Physics of semiconductor devices. 2nd ed. New York (NY): Wiley; 1981.
   Google Scholar
• Pierret RF. Semiconductor device fundamentals. 2nd ed. New Jersey (NJ): Addison Wesley; 1996.
   Google Scholar
• Brews JR. An improved high-frequency MOS capacitance formula. J. Appl. Phys. 1974;45:1276–1279.10.1063/1.1663401
   Web of Science ®Google Scholar
• Young Brian. Digital signal integrity modeling and simulation with interconnects and packages. New Jersey (NJ): Prentice Hall PTR; 2001.
   Google Scholar