62
Views
0
CrossRef citations to date
0
Altmetric
Original Articles

Investigation of tunneling layer and inter-gate-dielectric engineered TaN floating gate memory

, , , , &
Pages 146-152 | Received 06 Jul 2015, Accepted 03 Feb 2016, Published online: 06 May 2016

References

  • K. Kianm, and J. Choi, Future Outlook of NAND Flash Technology for 40 nm Node and Beyond. IEEE Non-Volatile Semiconductor Memory Workshop pp 9–11 (2006).
  • J. D. Lee, S. H. Hur, and J. D. Choi, Effects of floating-gate interference on NAND flash memory cell operation. IEEE, Electron Device Letters 23, 264–266 (2002).
  • S. Raghunathan, T. Krishnamohan, K. Parat, and K. Saraswat, Investigation of ballistic current in scaled Floating-gate NAND FLASH and a solution. IEEE International Electron Devices Meeting pp 1–4 (2009).
  • G. S. Kar et al. Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology. IEEE International Electron Devices Meeting pp 221–224 (2012).
  • S. Jayanti, X. Y. Yang, R. Suri, and V. Misra, Ultimate scalability of TaN metal floating gate with incorporation of high-K blocking dielectrics for Flash memory applications. IEEE International Electron Devices Meeting pp 531–534 (2010).
  • P. Blomme et al. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology. IEEE Electron Device Letters 33, 333–335 (2012).
  • D. Wellekens, P. Blomme, M. Rosmeulen, T. Schram, A. Cacciato, I. Debusschere, and J. V. Houdt, An Ultra-Thin Hybrid Floating Gate Concept for Sub-20 nm NAND Flash Technologies pp 1–4 (2011).
  • P. Blomme, J. V. Houdt, Scalability study of fully planarized hybrid floating gate Flash memory cells with high-k IPD. IEEE International Memory Workshop pp 237 (2012).
  • J. D. Vos, L. Haspeslagha, M. Demand, K. Devriendt, D. Wellekens, S. Beckx, and J. V. Houdt, A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45 nm generations. IEEE International Conference on Integrated Circuit Design and Technology pp 1–4 (2006).
  • P. Blomme, J. D. Vos, A. Akheyat, L. Haspeslagha, J. V. Houdt, and K. D. Meye, Scalable Floating Gate Flash Memory Cell With Engineered Tunnel Dielectric and High-K (Al2O3) Interpoly Dielectric. IEEE Non-Volatile Semiconductor Memory Workshop pp 52–53 (2006).
  • G. X. Chen, Z. L. Huo, L. Jin, Y. L. Han, X. K. Li, S. Liu, and M. Liu, Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier. IEEE Electron Device Letters 35, 744–746 (2014).
  • T. Lee, H. K. Ko, Y. Kim, J. Ahn, Y. B. Kim, K. S. Kim, and D. K. Choi, Thermal and Electrical Properties of TaN Electrode on HfO2 Gate Dielectric. Journal-Korean Physical Society 45, 1308–1312 (2004).
  • J M Z. Tseng, T. Pedron, A new method to extract gate coupling ratio and oxide trapped charge in flash memory cell. Microelectronic engineering 83, 218–220 (2006).

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.