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Technical Paper

Power Aware Channel Width Tapering of Serially Connected MOSFETs

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Pages 35-42 | Received 30 Jun 2007, Accepted 14 May 2008, Published online: 22 Sep 2015

References

  • Choudhary, S. & Qureshi, S. 2008, Australian Journal of Electrical & Electronics Engineering, Vol. 5, No. 1, pp. 35–42.
  • Cherkauer, B. S. & Friedman, E. G. 1994, “Channel width tapering of serially connected MOSFET’s with emphasis on power dissipation”, IEEE Trans. Very Large Scale of Integration (VLSI) Systems, March, Vol. 2, No. 1, pp. 100–114.
  • Choudhary, S. & Qureshi, S. 2007, “Power aware channel width tapering of serially connected MOSFETs”, IEEE International Conf. on Microelectronics, December, pp. 412–415.
  • Ding, L. & Mazumdar, P. 2001, “On optimal tapering of FET chains in high-speed CMOS circuits”, IEEE
  • Trans.Circuits and Systems, December, Vol. 48, No.12, pp. 1099–1109.
  • Shoji, M. 1985, “FET scaling in domino CMOS gates”, IEEE J. Solid-state Circuits, October, Vol. SC-20, pp. 1067–1071.

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