References
- Abdel-Hafeez, S., & Harb, S. (2006). A VLSI high-performance priority encoder using standard CMOS library. IEEE transactions on Circuits and Systems II: Express Briefs, 53, 597–601. doi:10.1109/TCSII.2006.876412
- Delgado-Frias, J. G., & Nyathi, J. (2000). A high-performance encoder with priority lookahead. IEEE transactions on Circuits and Systems I: Fundamental Theory and Applications, 47, 1390–1393. doi:10.1109/81.883335
- Delgado-Frias, J. G., Nyathi, J., & Summerville, D. H. (1998). A programmable dynamic interconnection network router with hidden refresh. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 45, 1182–1190. doi:10.1109/81.735440
- Hashemian, R. (1989). A high speed compact priority encoder. Proceedings 32nd IEEE Midwestern Symposium on Circuits and Systems, 1, 197–200. doi:10.1109/MWSCAS.1989.101828
- Hashemian, R. (1991). Highly parallel increment/decrement using CMOS technology. Proceedings 33rd IEEE Midwestern Symposium on Circuits and Systems, 2, 866–869. doi:10.1109/MWSCAS.1990.140858
- Huang, C. H., & Wang, J. S. (2003). High-performance and power-efficient CMOS comparators. IEEE Journal of Solid-State Circuits, 38, 254–262. doi:10.1109/JSSC.2002.807409
- Huang, C. H., Wang, J. S., & Huang, Y. C. (2002). Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. IEEE Journal of Solid-State Circuits,37, 63–76. doi:10.1109/4.974546
- Huang, S.-W., & Chang, Y.-J. (2010). A full parallel priority encoder design used in comparator. Proceedings 53rd IEEE International Midwest Symposium on Circuits and Systems, Washington, USA, 877–880. doi: 10.1109/MWSCAS.2010.5548664
- Kadota, H., Miyake, J., Nishimichi, Y., Kudoh, H., & Kagawa, K. (1985). An 8-kbit content-addressable and reentrant memory. IEEE Journal of Solid-State Circuits, 20, 951–957. doi:10.1109/JSSC.1985.1052420
- Kun, C., Quan, S., & Mason, A. (2004). A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead. Proceedings IEEE International Symposium on Circuits and Systems, Vancouver, Canada, 2, 753–756. doi:10.1109/ISCAS.2004.1329381
- Mohanraj, J., Balasubramanian, P., & Prasad, K. (2012). Power, delay and area optimized 8-bit CMOS priority encoder for embedded applications. Proceedings 10th International Conference on Embedded Systems and Applications, Nevada, USA, 111–113. doi:10.13140/2.1.2429.5681
- Wang, J. S., & Huang, C. H. (2000a). A high-speed single-phase-clocked CMOS priority encoder. Proceedings IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, 5, 537–540. doi:10.1109/ISCAS.2000.857490
- Wang, J. S., & Huang, C. H. (2000b). High-speed and low-power CMOS priority encoders. IEEE Journal of Solid-State Circuits, 35, 1511–1514. doi:10.1109/4.871331