References
- Chang, S.-C., Ceyhan, A., Kumar, V., & Naeemi, A. (2014). Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits. Proceedings of the 2014 International Symposium on Low Power Electronics and Design - ISLPED ’14, 63–68. https://doi.org/10.1145/2627369.2631638
- Ismail, Y. I., & Friedman, E. G. (2000). Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(2), 195–206. https://doi.org/10.1109/92.831439
- Karthikeyan, A., & Mallick, P. S. (2017). Transmission gate as buffer for carbon-nanotube- based VLSI interconnects. IETE Journal of Research, 64(2), 296–305. https://doi.org/10.1080/03772063.2017.1351316
- Karthikeyan, A., & Mallick, P. S. (2019). Body-biased subthreshold bootstrapped CMOS driver. Journal of Circuits, Systems and Computers, 28(3), 1950051. https://doi.org/10.1142/S0218126619500518
- Khursheed, A., Khare, K., & Haque, F. Z. (2019). Designing of ultra-low-power high-speed repeaters for performance optimization of VLSI interconnects at 32 nm. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 32(2), 1–16. https://doi.org/10.1002/jnm.2516
- Li, W., Zhao, W., Liu, P., Wang, J., & Wang, G. (2020). Optimal repeater insertion for horizontal and vertical graphene nanoribbon interconnects. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 33(2), 1–14. https://doi.org/10.1002/jnm.2696
- Liang, F., Wang, G., & Ding, W. (2011). Estimation of time delay and repeater insertion in multiwall carbon nanotube interconnects. IEEE Transactions on Electron Devices, 58(8), 2712–2720. https://doi.org/10.1109/TED.2011.2154334
- Liu, P.-W., Zhao, W.-S., Wang, D.-W., Wang, J., Hu, Y., & Wang, G. (2020). Optimal repeater insertion for nano-interconnects in current-mode signalling scheme. Micro & Nano Letters, 15(5), 308–312. https://doi.org/10.1049/mnl.2019.0765
- Lu, Q., Zhu, Z., Yang, Y., & Ding, R. (2016). Analysis of propagation delay and repeater insertion in single-walled carbon nanotube bundle interconnects. Microelectronics Journal, 54(8), 85–92. https://doi.org/10.1016/j.mejo.2016.05.012
- Sathyakam, P. U., Banerjee, A., & Mallick, P. S. (2020). Performance analysis of square and triangular CNT bundle interconnects driven by CNTFET-based inverters. Proceedings of the 3rd ICMETE, Micro-Electronics and Telecommunication Engineering, 317–324. https://doi.org/10.1007/978-981-15-2329-8_32
- Sathyakam, P. U., Mallick, P. S., & Saxena, A. A. (2019). High-speed sub-threshold operation of carbon nanotube interconnects. IET Circuits, Devices & Systems, 13(4), 526–533. https://doi.org/10.1049/iet-cds.2018.5118
- Vyas, A. A., Zhou, C., & Yang, C. Y. (2018). On-chip interconnect conductor materials for end-of-roadmap technology nodes. IEEE Transactions on Nanotechnology, 17(1), 4–10. https://doi.org/10.1109/TNANO.2016.2635583
- Zhao, W., Member, S., Liu, P., Yu, H., & Hu, Y. (2019). Repeater insertion to reduce delay and power in copper and carbon nanotube-based. IEEE Access, PP(c), 7, 13622–13633. https://doi.org/10.1109/ACCESS.2019.2893960