Design and evaluation of an efficient parity-preserving reversible QCA gate with online testability

References

• Angizi, S., Alkaldy, E., Bagherzadeh, N., & Navi, K. (2014). Novel robust single layer wire crossing approach for exclusive OR sum of products logic design with quantum-dot cellular automata. Journal of Low Power Electronics, 10(2), 259–271.10.1166/jolpe.2014.1320
   Google Scholar
• Bennett, C. H. (1973). Logical reversibility of computation. IBM Journal of Research and Development, 17(6), 525–532.10.1147/rd.176.0525
   Web of Science ®Google Scholar
• Chabi, A. M., Roohi, A., Khademolhosseini, H., Sheikhfaal, S., Angizi, S., Navi, K., & DeMara, R. F. (2016). Towards ultra-efficient QCA reversible circuits. Microprocessors and Microsystems, 49, 127–138.
   Web of Science ®Google Scholar
• Das, J. C., & De, D. (2016a). Reversible comparator design using quantum dot-cellular automata. IETE Journal of Research, 62(3), 323–330.10.1080/03772063.2015.1088407
   Web of Science ®Google Scholar
• Das, J. C., & De, D. (2016b). Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication. Frontiers of Information Technology & Electronic Engineering, 17(3), 224–236.
   Web of Science ®Google Scholar
• Fredkin, E., & Toffoli, T. (1982). Conservative logic. International Journal of Theoretical Physics, 21(3), 219–253.10.1007/BF01857727
   Web of Science ®Google Scholar
• Goswami, M., Sen, B., Mukherjee, R., & Sikdar, B. K. (2017). Design of testable adder in quantum-dot cellular automata with fault secure logic. Microelectronics Journal, 60, 1–12.10.1016/j.mejo.2016.11.008
   Web of Science ®Google Scholar
• Hari, S. K. S., Shroff, S., Mahammad, S. N., & Kamakoti, V. (2006). Efficient building blocks for reversible sequential circuit design. Circuits and Systems, 2006. MWSCAS’06. 49th IEEE International Midwest Symposium on (Vol. 1). IEEE.
   Google Scholar
• Hennessy, K., & Lent, C. S. (2001). Clocking of molecular quantum-dot cellular automata. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 19(5), 1752–1755.10.1116/1.1394729
   Web of Science ®Google Scholar
• Karkaj, E. T., & Heikalabad, S. R. (2016). A testable parity parity-preserving gate in quantum-dot cellular automata. Superlattices and Microstructures.
   Web of Science ®Google Scholar
• Karkaj, E. T., & Heikalabad, S. R. (2017). Binary to gray and gray to binary converter in quantum-dot cellular automata. Optik-International Journal for Light and Electron Optics, 130, 981–989.10.1016/j.ijleo.2016.11.087
   Google Scholar
• Landauer, R. (1961). Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, 5(3), 183–191.10.1147/rd.53.0183
   Web of Science ®Google Scholar
• Lent, C. S., & Isaksen, B. (2003). Clocked molecular quantum-dot cellular automata. IEEE Transactions on Electron Devices, 50(9), 1890–1896.10.1109/TED.2003.815857
   Web of Science ®Google Scholar
• Ma, X., Huang, J., Metra, C., & Lombardi, F. (2008). Reversible gates and testability of one dimensional arrays of molecular QCA. Journal of Electronic Testing, 24(1–3), 297–311.10.1007/s10836-007-5042-2
   Web of Science ®Google Scholar
• Misra, N. K., Sen, B., & Wairya, S. (2017). Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits. Journal of Computational Electronics, 16(2), 442–458.10.1007/s10825-017-0960-4
   Web of Science ®Google Scholar
• Misra, N. K., Wairya, S., & Sen, B. (2017). Design of parity-preserving, reversible sequential logic for cost efficient emerging nano circuits with enhanced testability. Ain Shams Engineering Journal.
   Web of Science ®Google Scholar
• Momenzadeh, M., Ottavi, M., & Lombardi, F. (2005). Modeling QCA defects at molecular-level in combinational circuits. Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on. IEEE.
   Google Scholar
• Ottavi, M., Schiano, L., Lombardi, F., & Tougaw, D. (2006). HDLQ: A HDL environment for QCA design. ACM Journal on Emerging Technologies in Computing Systems (JETC), 2(4), 243–261.10.1145/1216396
   Google Scholar
• Parhami, B. (2006). Fault-tolerant reversible circuits. Signals, Systems and Computers, 2006. ACSSC’06. Fortieth Asilomar Conference on. IEEE.
   Google Scholar
• Roohi, A., Zand, R., Angizi, S., & Demara, R. F. (2016). A parity-preserving reversible QCA gate with self-checking cascadable resiliency. IEEE Transactions on Emerging Topics in Computing, 1, 1–1.10.1109/TETC.2016.2593634
   Web of Science ®Google Scholar
• Sasamal, T. N., Singh, A. K., & Ghanekar, U. (2016). Design of non-restoring binary array divider in majority logic-based QCA. Electronics Letters, 52(24), 2001–2003.10.1049/el.2016.3188
   Web of Science ®Google Scholar
• Sen, B., Dutta, M., Goswami, M., & Sikdar, B. K. (2014). Modular design of testable reversible ALU by QCA multiplexer with increase in programmability. Microelectronics Journal, 45(11), 1522–1532.10.1016/j.mejo.2014.08.012
   Web of Science ®Google Scholar
• Sen, B., Dutta, M., & Sikdar, B. K. (2014). Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing. Microelectronics Journal, 45(2), 239–248.10.1016/j.mejo.2013.11.008
   Web of Science ®Google Scholar
• Sen, B., Dutta, M., Some, S., & Sikdar, B. K. (2014). Realizing reversible computing in QCA framework resulting in efficient design of testable ALU. ACM Journal on Emerging Technologies in Computing Systems (JETC), 11(3), 30.
   Web of Science ®Google Scholar
• Sen, B., Saran, D., Saha, M., & Sikdar, B. K. (2011). Synthesis of reversible universal logic around QCA with online testability. In Electronic System Design (ISED), 2011 International Symposium on. IEEE
   Google Scholar
• Singh, G., Sarin, R. K., & Raj, B. (2016). A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis. Journal of Computational Electronics, 15(2), 455–465.10.1007/s10825-016-0804-7
   Web of Science ®Google Scholar
• Srivastava, S., Asthana, A., Bhanja, S., & Sarkar, S. (2011). QCAPro-an error-power estimation tool for QCA circuit design. Circuits and Systems (ISCAS), 2011 IEEE International Symposium on. IEEE.
   Google Scholar
• Thapliyal, H., & Ranganathan, N. (2009). Parity-preserving QCA gate (CQCA) for designing concurrently testable molecular QCA circuits. VLSI Design, 2009 22nd International Conference on. IEEE.
   Google Scholar
• Thapliyal, H., Ranganathan, N., & Kotiyal, S. (2013). Design of testable reversible sequential circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(7), 1201–1209.10.1109/TVLSI.2012.2209688
   Web of Science ®Google Scholar
• Toffoli, T. (1980). Reversible computing. Automata, Languages and Programming, 632–644.
   Google Scholar
• Walus, K., Dysart, T. J., Jullien, G. A., & Budiman, R. A. (2004). QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata. IEEE Transactions on Nanotechnology, 3(1), 26–31.10.1109/TNANO.2003.820815
   Web of Science ®Google Scholar
• Zhang, R., Walus, K., Wang, W., & Jullien, G. A. (2004). A method of majority logic reduction for quantum cellular automata. IEEE Transactions on Nanotechnology, 3(4), 443–450.10.1109/TNANO.2004.834177
   Web of Science ®Google Scholar