Development and design of an FPGA-based encoder for NPN

References

• Aitkhozhayeva, Y., & Tynymbayev, S. (2014). Aspects of hardware modulation in asymmetric cryptography. Journal Vestnik NAS RK, 5, 88–14. ISSN-. https://www.kaznu.kz/content/files/pages/folder23401/%D0%92%D0%B5%D1%81%D1%82%D0%BD%D0%B8%D0%BA_05_2014_%D0%9D%D0%90%D0%9D%D0%A0%D0%9A.pdf#page=88
   Google Scholar
• Barrera, A., Cheng, C.-W., & Kumar, S. (2020, June 24–26). A fast implementation of the Rijndael substitution box for cryptographic AES. In Proceedings - 2020 3rd international conference on data intelligence and security (Vol. 9323014, pp. 20–25). South Padre Island, TX: IEEE. https://doi.org/10.1109/icdis50059.2020.00009
   Google Scholar
• Gnatyuk, S., Okhrimenko, A., Kovtun, M., Gancarczyk, T.,&Karpinskyi, V. (2016, October 16–19). Method of algorithm building for modular reducing by irreducible polynomial. In Proceedings of the 16th international conference on control, automation and systems (pp. 1476–1479). Gyeongju, Korea (South): IEEE. https://doi.org/10.1109/iccas.2016.7832498
   Google Scholar
• Kalimoldayev,M., Tynymbayev,S., Gnatyuk,S., Ibraimov,M.,&Magzom,M.(2020). The device for multiplying polynomials modulo an irreducible polynomial. News of the National Academy of Sciences of the Republic of Kazakhstan Series of Geology and Technical Sciences, 2(434), 199–205. https://doi.org/10.32014/2020.2518-170X.60
   Google Scholar
• Kalimoldayev, M., Tynymbayev, S., Gnatyuk, S., Magzom, M., Khokhlov, S., & Kozhagulov, Y. (2020). Matrix multiplier of polynomials modulo analysis starting with the lower order digits of the multiplier NEWS of the Academy of Sciences of the Republic of Kazakhstan Series of Geology and Technical Sciences. News of the National Academy of Sciences of the Republic of Kazakhstan, 4(436), 181–187. https://doi.org/10.32014/2019.2518-170X.113
   Google Scholar
• Kalimoldayev, M., Tynymbayev, S., Magzom, M., Ibraimov, M., Khokhlov, S., Abisheva, A., & Sydorenko, V. (2019, June 12). Polynomials multiplier under irreducible polynomial module for highperformance cryptographic hardware tools. In CEUR workshop proceedings. 15th international conference on ICT in education, research and industrial applications. Integration, harmonization and knowledge transfer, ICTERI 2019 (Vol. 2393, pp.729–737). Kherson.
   Google Scholar
• Krishna, B. M., Khan, H., Madhumati, G. L., Kumar, K. P., Tejaswini, G., Srikanth, M., & Ravali, P. (2017). FPGA implementation of DES algorithm using DNA cryptography. Journal of Theoretical and Applied Information Technology, 95(10), 2147–2158. https://www.scopus.com/record/display.uri?eid=2-s2.0-85020191255&origin=resultslist&sort=plf-f&src=s&sid=8091300ea67e316acead5bc399fd321d&sot=b&sdt=b&sl=75&s=TITLE-ABS-KEY%28FPGA+implementation+of+DES+algorithm+using+DNA+cryptography.%29&relpos=0&citeCnt=3&searchTerm=
   Google Scholar
• Kumar, A., Vishnoi, P., & Shimi, S. L. (2019). Smart grid security with cryptographic chip integration. EAI Endorsed Transactions on Energy Web, 19(23), 6. https://doi.org/10.4108/eai.13-7-2018.157037
   Google Scholar
• Kumar, N., Mishra, V. M., & Kumar, A. (2021). Smart grid and nuclear power plant security by integrating cryptographic hardware chip. Nuclear Engineering and Technology, 53(10), 3327–3334. https://doi.org/10.1016/j.net.2021.05.006
   Web of Science ®Google Scholar
• Liu, W., Fan, S., Khalid, A., Rafferty, C., & O’Neill, M. (2019). Optimized schoolbook polynomial multiplication for compact lattice-based cryptography on FPGA. In IEEE transactions on Very Large Scale Integration (VLSI) systems (Vol. 27(10), pp. 2459–2463). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1109/tvlsi.2019.2922999
   Google Scholar
• Nedjah, N., & de Macedomourelle, L. (2006). A review of modular multiplication methods and respective hardware implementations. Informatica, 30(1), 111–129 https://www.scopus.com/record/display.uri?eid=2-s2.0-33244487252&origin=resultslist&sort=plf-f&src=s&sid=14e19744d3164b83e97af2029c0edc5e&sot=b&sdt=b&sl=97&s=TITLE-ABS-KEY%28A+review+of+modular+multiplication+methods+and+respective+hardware+implementations%29&relpos=0&citeCnt=37&searchTerm=.
   Google Scholar
• RyabkoB, Y., & Fionov, A. I. (2004). Osnovy sovremennoy kriptografii dlya specialistov v informacionnyh technologiyah. Nauchnyi Mir, 173 s (in Russ.).
   Google Scholar
• Sadiq, M., & Ahmed, J. (2006). Complexity analysis of multiplication of long integers. Asian Journal of Information Technology, 5(2), 111–112. https://doi.org/10.1109/sbcci.2002.1137629
   Google Scholar
• Saini, R., Jain, M., & Suneja, K. (2020). FPGA Based Design of Speech Encryption and Decryption for Secure Communication. Communications in Computer and Information Science, 1170, 37–49. ISSN: . https://doi.org/10.1007/978-981-15-9671-1_3
   Google Scholar
• Shan`gin, V. E. (2007). Zashitainformacii v kompiuternyhsistemahisetyah. DMK Press. 592 s. (in Russ).
   Google Scholar
• Tenca, A. F., & Tawalbeh, L. A. (2003). Algorithm for Unified Modular Division in GF(p) and GF(2n) Suitable for Cryptographic Hardware. Electronics Letters, 40(5), 304–306. https://doi.org/10.1049/el:20040233
   Web of Science ®Google Scholar
• Wollinger, T., Guajardo, J., & Paar, C. (2004). Cryptography on FPGAs: State of the art implementations and attacks, In Special issue on embedded systems and security of the ACM Transactions in Embedded Computing Systems (TECS) (Vol. 3). ACM Transactions on Embedded Computing Systems. https://doi.org/10.1145/1015047.1015052
   Google Scholar
• Zambreno, J., Honbo, D., Choudhary, A., Simha, R., & Narahari, B. (2006). High performance software protection using reconfigurable architectures. In Proceedings of the IEEE (Vol. 94( 2)). IEEE. https://doi.org/10.1109/jproc.2005.862474
   Google Scholar