References
- D K Slisher, R G Filippi Jr., D W Storaska, and A H Gay “Scaling of Si MOSFETs for Digital Applications”, Final Project in the “Advanced Concepts in Electronic and Optoelectronic Devices, 1999.
- V Kilchytska, T M Chung, B Olbrechts, Y Vovk, J P Raskin, and D Flandre, “Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity” Solid State Electron, Vol. 51, pp. 1238–44, 2007.
- C H Shih, Y M Chen, and C Lien, “An insulated shallow extension structure for bulk MOSFET” IEEE Trans. On Electron. Devices, Vol. 50, pp. 2294–7, 2003.
- V Kumari, M Saxena, R S Gupta, and M Gupta, “Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications” Microelectronics Reliability, Vol. 52, no. 8, pp. 1610–2, 2012.
- V Kumari, M Saxena, R S Gupta, and M Gupta, “Temperature Dependent Drain Current Model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET For Wide Operating Temperature Range” Microelectronics Reliability, Vol. 52, pp. 974–83, 2012.
- ECE 334-Lecture 21nMOs-current and transmission gates.
- S Harrison, D Munteanu, J L Autran, A Cros, R Cerutti, and T Skotnicki, “Electrical characterization and modeling of high-performance SON DG MOSFETs”, Solid-State Device Research conference, ESSDERC 2004. Proceeding of the 34th European, pp. 373–6, 2004.
- ATLAS: 3-D Device Simulator, SILVACO International, Version 5.14.0.R, 2010.
- U Ko, and P T Balsara, “High-performance energy efficient D flip-flop circuits,” IEEE Trans. on VLSI, Vol. 8, pp. 94–8, 2000.
- S Heo, R Krashinsky, and K Asanović, “Activity-sensitive flip-flop and latch selection for reduced energy,” Proc. ARVLSI, pp. 59–74, 2001.
- J Zhuge, A S Verhulst, W G Vandenberghe, W Dehaene, R Huang, and Y Wang, et al., “Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications”, Semiconductor Science and Technology, Vol. 26, pp. 085001, 2011(8pp).
- More on CMOS Circuit-Level Design, Supplement to Logic and Computer Design Fundamentals, Pearson Education 2008.
- A D Pathak, “MOSFET/IGBT Drivers theory and applications”, Applications note AN-401, pp.1–26, 2012.
- N H E Weste, A Banerjee and D Harris, “CMOS VLSI Design A circuit and systems perspective”, 3rd ed., Pearson, 2006.
- H Kang, J W Han, and Y K Choi, “Analytical threshold voltage model for double gate MOSFET with localized charges” IEEE electron device letters, Vol. 29, pp. 927–30, 2008.
- E G Ioannidis, A Tsormpatzoglou, D H Tassis, C A Dimitriadis, G Ghibaudo, and J Jomaah, “Effects of localized interface charges on the threshold voltage of short channel undoped symmetrical double gate MOSFET”, IEEE Trans on Electron Devices, Vol. 58, pp. 433–40, 2011.
- R J Baker, H W Li, and D E Boyce, “CMOS Circuit Design Layout, and Simulation,” Prentice Hall of India Pvt. Ltd; 2000.