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Abstract
In this paper, we deal with the problem of placement of a set of interconnected chips on the surface of a PCB. The solution we have suggested aims to place the chips on surface of the board so that its wireability gets enhanced. Moreover, our approach for solution of placement problem is so interlinked with the partitioning phase that the three sub-problems (i.e. Partitioning, Placement, Wire routing) of the logic circuit layout problem get integrated together which is a unique development. The computational complexity of the placement algorithm is O(n3i2).
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P. Pal Chaudhuri
Pal Chaudhuri, P (Dr): (b. Calcutta, 1941 Oct.) Obtained BE degree in Electrical Engineering from Bengal Engineering College in 1963. From 1963 to 1975, he was associated with IBM World Trade Corporation. In Sept., 1975 he joined IIT, Kharagpur as an Assistant Professor. He got his PhD degree in Engineering in 1979. Since January 1981, he is holding the post of Professor in Computer Science and Engineering. His research interests are design automation, well diagnosable system design and application of computer for medical diagnosis.