New Architecture of Fast Multiplier

Abstract

The scheme proposed in this paper is an endeavour to suggest an architecture for a fast multiplier keeping in view both the minimisation of time and component complexity. This scheme proposes the development of a faster multiplier chip than what is available in the commercial market in large numbers.

Indexing terms:

• cla
• csa
• F/A
• H/A
• ECL
• Wallance scheme
• Dadda scheme
• Dhwkadas scheme