Combinatorial Logic Synthesis using Technology Directed Decomposition

Abstract

The aim of logic synthesis is to produce circuits which satisfy the given boolean function while meeting timing constraints and requiring the minimum silicon area. Logic synthesis involves two steps namely logic decomposition and technology mapping. Existing methods treat the two as separate operation. The traditional approach is to minimize the number of literals without considering the target technology during the decomposition phase. The decomposed expressions are then mapped on to the target technology to optimize the area. Timing optimization is carried out subsequently. A new approach which treats logic decomposition and technology maping as a single operation is presented. The logic decomposition is based on the parameters of the target technology. The area and timing optimization is carried out during logic decomposition phase itself. Results using MCNC circuits are presented to show that this method produces circuits which are 38% faster while requiring 14% increase in area.

Indexing terms:

• VLSI design
• Combinatorial circuits
• Logic synthesis

Additional information

Notes on contributors

K Santeppa

K Santeppa obtained B Tech in Electronics and Communication engineering from J N T U College of Engineering, Anantapur and M Sc (Engg) in Computer Science and automation from Indian Institute of Science, Bangalore. He currently registered as a Ph D candidate in Electronics and Communication Engineering at Regional Engineering College, Warangal. He worked in Vikram Sarabhai Space Centre, Trivandrum from 1982 to 1988 in the field of microprocessor based realtime computer design for onboard and ground checkout systems for ASLV and PSLV. From 1988 onwards he has been working in the field of VLSI design at Advanced Numerical Research and Analysis Group (ANURAG), DRDO, Hyderabad. He has been involved in the development of several Application Specific Integrated Circuits (ASICs) including Microprocessors, DSP processors, floating point arithmetic processors etc. He received DRDO technology award in 1996 in recognition of his contributions towards development of 32-bit microprocessor “ANUPAMA”. He is currently Deputy Director of ANURAG coordinating VLSI design activities at

K Neelakantan

K Neelakantan obtained his B Tech in Electrical Engineering from IIT, Kanpur in 1976. He was awarded his M S & Ph D from IIT, Madras in 1981 and 1986 respectively.

After graduating from IIT, Kanpur, he joined the Indira Gandhi Centre for Atomic Research (IGCAR) at Kalpakkam in 1976. While at IGCAR he was involved in the design and development of electronic instruments and microprocessor based systems. He also worked on simulation of physical systems using digital and analog computers, signal to noise enhancement techniques, signal averaging etc. His research interests include studies in the role of noise in physical systems.

Dr Neelakantan joined DRDO in 1987 and helped set up the Advanced Numerical Research & Analysis Group (ANURAG) at Hyderabad. While at ANURAG, his research interests have been in the design and development of parallel processing systems and VLSI design. Dr Neelakantan has been the Director of ANURAG since 1992 Dr Neelakantan has published 26 research papers Conferences and Symposia. He was selected an Young Associate of the Indian Academy of Sciences in 1983. He has been selected for Om Prakash Bhasin Award, 1996 and the DRDO Scientist of the Year Award 1996.

V Rajaraman

V Rajaraman obtained B Sc (Hons) in Physics from Delhi University, DIISc and AIISc from the Indian Institute of Science, S M in Electrical Engineering from MIT and PhD from the University of Wisconsin. He taught at the University of Wisconsin, University of California, Berkeley, Indian Institute of Technology, Kanpur and Indian Institute of Science, Bangalore. He pioneered Computer Science Education and Research in India and in recognition was awarded Shanti Swarup Bhatnagar prize in 1976. He also received Homi Bhabha Prize awarded by the University Grants Commission, and the Om Prakash award in Electronics and Telecommunication. In 1998 he was conferred Padma Bhushan by the President of India and Syed Husain Zaheer Medal for excellence in Engineering Research by the Indian National Science Academy. Prof Rajaraman is a Fellow of the Computer Society of India, Indian National Academy of Engineering, Indian National Science Academy and the Indian Academy of Sciences. He is currently an IBM Research Professor in Information Technology at the Jawaharlal Nehru Centre for Advanced scientific Research and Hon Professor at Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore.