Partitioning based Approach for Finite State Machine State Encoding Targeting Low Power

Abstract

State encoding is one of the most crucial steps in the synthesis of finite state machines. Due to the enhanced emphasis on low power circuit design, state encoding strategies targeting low power consumption are sought after. Other approaches try to solve the problem by partitioning the FSM into two sub-FSMs, -this generally require larger register area. This paper utilizes the concept of state partitioning to solve the state-encoding problem. Experimental results show that even without physically partitioning the FSM into sub-FSMs, the scheme results in 48.89% power reduction over NOVA [1] and 26.64% lesser power than GA-D [2] which is directed towards low power state encoding.

Indexing terms:

• State encoding
• Low power
• FSM synthesis
• Optimal power minimised design

Additional information

Notes on contributors

P Nagamaheswara Reddy

Palem Nagamaheswara Reddy received his BTech degree in Computer Science and Engineering in 2001 from KSRM College of Engineering, Cuddapah, India. He received his MTech degree in Computer Science and Engineering from IIT Guwahati, in 2003. He is currently working as Assistant Systems Engineer in TATA Consultancy Services. His research interests include Finite State Machines and Low Power technologies.

Santanu Chattopadhyay

Santanu Chattopadhyay received his BE degree in Computer Science and Technology from Calcutta University in 1990. He received MTech in Computer & Information Technology and PhD in Computer Science from IIT Kharagpur in 1992 and 1996 respectively. He is currently an Associate Professor with the Department of Computer Science & Engineering NT Guwahati. His research interest include low power VLSI degign, Electronic CAD, testing, system-on-chip design and testing.