Zero Aliasing Space Compaction with Cellular Automata

Abstract

Complex integrated circuits produce voluminous test response data. Space compaction reduces the space requirement to store the response data by combining circuit outputs in certain fashion to reduce the number of outputs to be observed. In this paper, we present the design of a zero-aliasing space compactor that utilizes the theory of Cellular Automata based pattern classification to classify the fault-free and the faulty responses. Experimental results with the ISCAS85 benchmark circuits show that the scheme results in 1.26 time more compaction over the earlier zero-aliasing space compaction strategies. Area overhead of the proposed scheme is also much lesser.

Indexing terms:

• Built-in self test (BIST)
• Circuit-under-test (CLIT)
• User defined logic (UDL)
• Zero-aliasing

Additional information

Notes on contributors

Santanu Chattopadhyay

Santanu Chattopadhyay received his BE degree in Computer Science and Technology from Calcutta University (BE College) in 1990. He did his MTech in Computer and Information Technology and PhD in Computer Science & Engineering from Indian Institute of Technology, Kharagpur in 1992 and 1996 respectively. He is currently an Associate Professor in Computer Science & Engineering at Indian Institute of Technology, Guwahati. His research interest includes logic synthesis, testing, low power design, Cellular automata.

Prashant

Prashant received his BTech in Computer Science & Engineering from Indian Institute of Technology, Guwahati in 2001. His research interest includes Circuit Testing, Cellular Automata, etc.