REFERENCES
- K Saluja & M Karpovsky, Test Compression Hardware through Data Compression in Space and Time, in Proc Intl Test Conference, pp 83–88, 1983.
- J Hayes & A Friedman, Test Point Placement to Simplify Fault Detection, IEEE Trans on Computers, vol C-23, pp 727–735, July 1974.
- J Fox, Test-point Condensation in the Diagnosis of Digital Circuits, Proc of the IEE, vol 124, pp 89–94. February 1977.
- B Bhattacharya & A Dmitriev, Synthesis of Single-Output Space Compactors with Application to Scan-based IP Cores, in Proc ASPDAC, 2001.
- M Seuring & K Chakrabarty, Space Compaction of Test Responses of IP Cores using Orthogonal Transmission Functions, in IEEE VLSI Test Symposium, 2000.
- Y Li & J Robinson, Space Compaction Methods and Output Data Modification, IEEE Trans on CAD, vol 6, pp 290–294, March 1987.
- M Karpovsky & P Nagvajara, Optimal Time and Space Compression of Test Responses for VLSI Devices, in Procinti Test Conference, pp 523–529, 1987.
- S Reddy, K Saluja & M Karpovsky, A Data Compression Technique for Built-in Self-Test, IEEE Trans on Computers, vol C-37, pp 1151–1156, September 1988.
- W Jone & S Das, Space Compression Method for Built-in Self-Testing of VLSI Circuits, International Journal of Computer-Aided Design, vol 3, pp 309–322, September 1991.
- S Das, H Ho, W Jone & A Nayak, An improve Output Compaction Technique for Built-in Self-Test in VLSI Circuits, in Proc International Conference on VLSI Design, pp 403–407. 1995.
- M. A Ivanov, B Tsuji & V Zorian. Programmable HIST Space Compactors. IEEE Trans on Computers, vol 45, pp 1393–1404, December 1996.
- K Chakrabarty & J Hayes, Efficient Test Response Compression for Multiple Output Circuits, in Proc lull Test Conference, pp 501–510, 1994.
- K Chakrabarty, M Murray & J Hayes, Optimal Space Compaction of Test Responses, in Proc Intl Test Conference. pp 834–843, 1995.
- K Chakrabarty & J Hayes. Test Response Compaction using Multiplexed Parity Trees, IEEE Trans on CAD, vol 15, November 1996.
- H Pouya N Touba, Synthesis of Zero-Aliasing Elementary-Tree Space Compactors, in 16th IEEE VLSI Test Symposium, pp 70–77, 1988.
- S Chattopadhyay, D R Chowdhuri, S Bhattacharjee & PP Chaudhuri, Cellular automata array based diagnosis of board level faults, IEEE Trans on Computers, vol 47, pp 817–828, August 1998.
- J V Neuman, The theory of self-reproducing Automata. A W Burks ed Univ of Illinois Press, Urbana and London, 1966.
- S Wolfram, Statistical mechanics of cellular automata, Rev Mod Phys, vol 55, pp 601–644. July 1983.
- A K Das, Additive Cellular Automata: Theory and Application as a Built-in Self-test Structure. PhD thesis, NT Kharagpur, India. 1990.
- P P Chaudhuri, D R Chowdhury. S Nandi & S Chaitopadhyay, Additive Cellular Automata Theory and Applications: IEEE Computer Society, vol 1, 1997.
- D Chowdhury, S Chakraborty, B Vamsi & P Chaudhuri, Cellular Automata based synthesis of easily and fully testable FSMs, in Proc ICCAD'93, pp 650–653. Nov 1993.
- S Chattopadhyay, S Adhikari, S Sengupta & M Pal, Highly Regular, Modular and Cascadable Design of Cellular Automata based Pattern classifiers, IEEE Transactions on VLSI, vol 8, pp 724–735, December 2000.
- A K Das & P P Chaudhuri, Efficient characterization of cellular automata. Proc IEE Part E, vol 137, pp 81–87, January 1990.
- A K Das & P P Chudhuri, Vector space theoretic analysis of additive cellular automata and its applications for pseudo-exhaustive test pattern generation, IEEE Trans on Computers, vol 42, pp 340–352, March 1993.
- J L. Nielsen, BuDDy—Binary Decision Diagram Library Package version 2.0, in http:www.it-c.dk/research/huddy, 2001.
- E Brglez & H Fujiwara. A Neural Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran, in Proc of International Symposium on Circuits and Systems, pp 663–698, 1985.
- H Lee & D Ha, On the Generation of Test Patterns for Combinational Circuits, Tech Rep, 12–93, Department of Electrical Engg, Virginia Polytechnic Institute and Statr University, 1993.