Nanometer Scale Tunnel Oxide Fabricated by ‘Wet Nitrous Oxide Process’ for Non-Volatile memory Applications

Abstract

A new oxidation scheme, namely, 'Wet N₂O process' for the fabrication of tunnel oxide for flash memory applications has been developed and characterized using both aluminum gate MOS capacitors as well as poly gate MOS capacitors. The Al gate MOS capacitors were electrically characterized under constant field stress conditions for studying reliability and interface properties of the Wet N₂O oxide. The poly gate MOS capacitors are electrically characterized and the Stress Induced Leakage Current (SILC) of poly gate MOS capacitors were studied under constant current stress. The results obtained show that the 'Wet N₂O oxide' gives excellent interface characteristics and reliability compared to other oxides. The poly gate MOS capacitors show stability and J-E characteristics with extended Fowler-Nordheim region, high breakdown strength and extremely low SLIC when stressed with 35C/cm² and therefore ideally suited for application in flash memory devices with tunnel oxides in the nanometer thickness range of 6 nm to 7 nm.

Indexing terms:

• Tunnel oxides
• Nitridation
• Wet N₂O oxidation
• Flash memory devices

Additional information

Notes on contributors

K N Bhat

K N Bhat has been a Professor at IIT Madras, for over twenty years coordinating the Microelectronics and MEMS research activity in the EE Department. He has been the Principal Investigator of the Projects “MOS Integrated Piezoresistive polysilicon pressure sensors” and the “Micropump for Drug delivery and Drug Dosage Control” sponsored by the National Program on Smart Materials (NPSM).

He is an alumnus of IISc Bangalore, IIT Madras, and Rensselaer Polytechnic Institute Troy, New York. He was a Post Doctoral Research Associate in the ECSE Department of Renssellaer Polytechnic Institute, Troy, New York during 1979–1981 and a visiting Professor in the EE Department at the University of Washington, Seattle (USA) on Sabbatical leave from IIT Madras during the year 1999.

He has published over 175 papers, guided over 25 MS and PhD research scholars and over hundred BTech and MTech degree projects. His research interests include Silicon and Gallium Arsenide devices modeling and technology, Polycrystalline silicon and single crystal silicon SOI MOSFETs, Solar Cells and Micromachined Silicon Sensors and Actuators. Professor K N Bhat is a Fellow of the Indian National Academy of Engineering.

Naseer Babu P

Naseer Babu P received MTech degree in solid state technology, focusing on the research of ultra thin gate dielectric for the applications in deep submicron MOS transistors, from Indian Institute of Technology Madras, Chennai, India, in 2003. He received MSc and BSc degrees, majored in physics, from University of Calicut in 1998 and 2000 respectively. Currently he is pursuing towards the PhD degree at Indian Institute of Technology Madras focusing on the research of high quality tunnel oxide fabrication technology and its reliability studies for Flash Memory applications. His current research interest includes reliability studies of tunnel oxides, simulation and modeling of semiconductor devices and MEMS.