Process-Induced Delay Variation in SWCNT, MWCNT, and Mixed CNT Interconnects

ABSTRACT

This paper deals with an analysis of propagation delay in carbon nanotube (CNT) bundled interconnects under process-induced variations. An accurate and compact analytical model of mixed CNT bundle (MCB) is employed that takes into account the random distribution of CNTs having different diameters. Depending on the bundle configurations, a multi-conductor transmission line (MTL) model is presented for MCB, bundled SWCNT, and bundled MWCNT interconnects. The performance of CNT bundles is investigated under process-induced variations of temperature, metallic ratio, contact resistance, and bundle area. A driver-interconnect-load (DIL) system is used to perform the Monte Carlo simulations to analyze the impact of process-induced variations on propagation delay. It is observed that the MCB is more tolerant to the process variations for global interconnect lengths with respect to the bundled SWCNT and bundled MWCNT.

Keywords:

• Mixed carbon nanotube bundle (MCB)
• Equivalent RLC circuit model
• Process-induced variation
• Random distribution
• Propagation delay

ACKNOWLEDGEMENTS

The authors would like to thank Mr. Vobulapuram Ramesh Kumar, Indian Institute of Technology Roorkee, India, for many useful discussions and feedback.

Additional information

Notes on contributors

Manoj Kumar Majumder

Manoj Kumar Majumder received his BTech and MTech degrees in 2007 and 2009, respectively. Recently, he has submitted his PhD thesis to Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, India. He is currently associated with the academic activities in Electronics and Communication Engineering Department in Techno India University, Kolkata, West Bengal, India. His current research interests are in the area of Carbon Nanotube and Graphene nanoribbon based VLSI interconnects and vias.

Email: [email protected]

Jainender Kumar

Jainender Kumar received his BTech and MTech degrees from ABES Engineering College, Ghaziabad, India, and Indian Institute of Technology, Roorkee, India, in 2010 and 2013, respectively. Currently, he is working as an IP researcher in semiconductor domain and looking in patents related to memories, MOSFETs, FinFET, packaging, analogue circuits, etc. His research interest includes Carbon Nanotube based VLSI interconnects and circuit modelling.

Email: [email protected]

Brajesh Kumar Kaushik

Brajesh Kumar Kaushik received his PhD degree from Indian Institute of Technology, Roorkee, India, in 2007. He is currently working as an associate professor in Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, India. He has authored several high-quality research papers in different peer-reviewed international journals and reputed international conferences.

Dr. Kaushik is a member of many expert committees constituted by Government and Non-Government organizations. He has also received many awards and recognitions from International Biographical Center (IBC), Cambridge, etc. His name has been listed in Marquis Who's Who in Science and Engineering® and Marquis Who's Who in the World®. His research interests are in the areas of High Speed Interconnects, Low power VLSI Design, Carbon Nanotube based Designs, Organic Electronics, FinFET Device Circuit Co-Design, Electronic Design Automation (EDA), Spintronics based devices and circuits.

Email: [email protected]