Test Architecture Optimization for Post-bond Test and Pre-bond Tests of 3D SoCs Using TAM Reuse

ABSTRACT

Three-dimensional (3D) integration based on through-silicon-via (TSV) is an emerging technology. It provides reduced interconnection length, heterogeneous integration, higher performance, and bandwidth. However, 3D design poses several challenges and testing of 3D integrated circuits (ICs) is a key challenge. So, effective test mechanisms are necessary to test this new generation chip. In this paper, we address test architecture optimization and test schedule for 3D System-on-Chip (SoC). A novel heuristic is suggested to minimize the post-bond test time of 3D SoC under the constraints of TSV and power consumption. Also, the total test time is minimized by considering the routing cost of test access mechanisms (TAMs). We minimize the TAM wire length by sharing TAM segments in pre-bond tests and post-bond test. Simulations are carried out on different ITC'02 test benchmarks that demonstrate the efficiency of the proposed method.

KEYWORDS:

• Post-bond test
• Pre-bond test
• SoC
• TAM
• TSVs

Additional information

Notes on contributors

Surajit Kumar Roy

Surajit Kumar Roy received the BSc (Hons in physics) from Calcutta University, India. He also received Bachelor of Technology in computer science and engineering and subsequently Master of Technology in computer science and engineering from Calcutta University, India, in 2002 and 2004. He was awarded PhD degree from Indian Institute of Engineering Science and Technology (IIEST), Shibpur, Howrah, WB India in 2016. Currently, he is working at Indian Institute of Engineering Science and Technology, India, as assistant professor in the department of Information Technology. His research interest includes VLSI testing, embedded systems, and hardware security.

Chandan Giri

Chandan Giri has been at Indian Institute of Engineering Science and Technology, Shibpur, Howrah, WB, India since 2008 as assistant professor, Department of Information Technology. His current research is focused on testing and design-for-testability of integrated circuits (especially 3D and multicore chips) and wireless sensor network. His research project included 3D multicore IC testing. Research support is provided by the University Grant Commission, Government of India. C Giri received his Bachelor of Technology (BTech) in computer science and engineering from Calcutta University, India, in 2000 and subsequently Masters of Engineering (ME) in computer science and engineering from Jadavpur University, Kolkata, India, in 2002. He was awarded PhD degree from Department of Electronics and Electrical Communication Engineering of Indian Institute of Technology, Kharagpur, in 2008. He also presented his research papers in several international conferences. He is a member of IEEE and ACM. Email: [email protected]