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Articles

Test Architecture Optimization for Post-bond Test and Pre-bond Tests of 3D SoCs Using TAM Reuse

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References

  • H. Loh, Y. Xie, and B. Black, “Processor design in 3D die-stacking technologies,” Proc. IEEE Micro, Vol. 27, pp. 31–48, 2007.
  • K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICS: A novel chip design for improving deep sub-micrometer interconnect performance and system-on-chip integration,” Proc. IEEE, Vol. 89, no. 5, pp. 602–33, 2001.
  • W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3DICs:The pros and cons of going vertical,” IEEE Des. Test Comput., Vol. 22, no. 6, pp. 498–510, 2005.
  • H. S. Lee, and K. Chakrabarty, “Test challenges for 3D integrated circuits,” IEEE Design and Test of Computers, Special Issue on 3D IC Design and Test, Vol. 5, 26–35, 2009.
  • V. Iyengar, and K. Chakraborty, “Test wrapper and test access mechanism co-optimization for system-on-chip,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 18, pp. 213–30, 2002.
  • E. J. Marinissen, “Challenges in testing TSV-based 3D stacked ICs: Test Flows, test Contents, and test access,” in Proc. of IEEE Asia-Pacific Conference on circuits and Systems, 2010, pp. 544–7.
  • S. K. Roy, S. Ghosh, H. Rahaman, and C. Giri, “Test wrapper design for 3D system-on-chip using optimized number of TSVs,” Proc. IEEE Intl. Symp. Electr. Syst. Des., 197–202, 2010.
  • B. Noia, K. Chakrabarty, and Y. Xie, “Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs,” in Proc. of IEEE International Conference on Computer Design, 2009, pp. 70–7.
  • X. Wu, Y. Chen, K. Chakrabarty, and Y. Xie, “Test access mechanism optimization for core-based three-dimensional SoCs,” Microelectron. J., Vol. 41, no. 10, pp. 601–15, 2010.
  • L. Jiang, L. Huang, and Q. Xu, “Test architecture design and optimization for three-dimensional SoCs,” Proc. Des. Autom. Test in Europe (DATE), 220–5, 2009.
  • E. J. Marinissen, J. Verbree, and M. Konijnenburg, “A structured and scalable test access architecture for TSV-based 3D stacked ICs,” in Proc. of VLSI test Symposium, 2010, pp. 269–74.
  • B. Noia, K. Chakrabarty, and E. J. Marinissen, “Optimization methods for post-bond testing of 3D stacked ICs,” J. Electr. Test., Vol. 28, no. 1, pp. 102–20, 2012.
  • B. Noia, K. Chakrabarty, and E. J. Marinissen, “Test architecture optimization for TSV based 3D-stacked ICs,” in Proc. of 15th IEEE ETS, 2010, pp. 24–9.
  • B. Noia, K. Chakrabarty, S. K. Goel, E. J. Marinissen, and J. Verbree, “Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs,” IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., Vol. 30, no. 11, pp. 1705–18, 2011.
  • L. Jiang, L. Huang, Q. Xu, K. Chakrabarty, and T. M. Mak, “Integrated test-architecture optimization and thermal-aware test scheduling for 3-D SoCs under pre-bond test-pin-count constraint,” IEEE Trans. VLSI Syst., Vol. 20, no. 9, pp. 1621–33, 2012.
  • S. K. Roy, S. Chatterjee, C. Giri, and H. Rahaman, “Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing,” in Proc. of 3DIC, 2013, pp. 1–4.
  • L. Jiang, and D. Xiang, “Dft optimization for pre-bond testing of 3D-SICs containing TSVs,” in Proc. International Conference on computer design (ICCD), 2010, pp. 474–9.
  • L. Jiang, Q. Xu, and B. Eklow, “On effective TSV repair for 3D-stacked ICs,” in Proc. of DATE, 2012, pp. 793–8.
  • S. K. Roy, P. Ghosh, H. Rahaman, and C. Giri. “Session-based core test scheduling for 3D SOCs”, in Proc. of ISVLSI, 2014, pp.196–201.
  • S. K. Roy, and C. Giri. “Design-for-test and test time optimization for 3D SOCs”, in Proc. of ITC, 2017, pp. 1–10.
  • K. Chakraborty, and E. J. Marinissen, “Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip,” IEEE Trans. Computer, Vol. 52, no. 12, pp. 1619–32, 2003.
  • S. Banerjee, S. Majumder, and B. B. Bhattacharya, “Test-time reduction for power-aware 3D-SoC,” in Proc. of VLSI Design, 2018, pp. 103–8.
  • T. Kaibartta, C. Giri, H. Rahaman, and D. K. Das, “Optimizing test time for core-based 3-D,” in Proc. of ASQED, 2015, pp. 62–7.
  • J. Pouget, E. Larsson, and Z. Peng, “Multiple-constraint driven system-on-chip test time optimization,” J. Electr. Test. Theory Appl. (JETTA), Vol. 21, no. 6, pp. 599–611, 2005.

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