CMOS Implementation of a Novel High Speed 4:2 Compressor for Fast Arithmetic Circuits

Abstract

This paper deals with the design and analysis of a new 4-2 compressor which can be used in high-speed multipliers. The proposed compressor features eliminated glitch at the output waveform. By optimum tuning of the width of the transistors, C_out is produced more quickly, and therefore higher operating speeds can be achieved. The effect of process variation on the circuit has been studied and a new structure is proposed to overcome the effect of process variation by utilizing a reference voltage generator circuit. A 32 × 32-bit multiplier has been developed utilizing these compressors in order to evaluate the new compressor in a practical environment. The total multiplier circuit was simulated with HSPICE simulator (BSIM3v3 parameters) using CMOS standard cell library of 0.18 µm and the Layouts were extracted with Cadence Virtuoso v 5.1 Layout Plus tool. The simulation results represent 185 × 10⁻³ pj Power-Delay-Product (PDP) and 40 pj × ps Energy Delay Product (EDP) with 221 ps delay from input to output.

KEYWORDS:

• Adders
• Compressors
• Digital circuits
• Layout
• Logic circuits
• Multiplying circuits
• Very high speed integrated circuits

Additional information

Notes on contributors

M. Ghasemzadeh

Mehdi Ghasemzadeh was born in Urmia, Iran in 1988. He received the BS and MS degrees in electrical engineering from Urmia University, Urmia, Iran in 2012 and 2014, respectively (all with honors). He is currently working towards PhD honors degree in electrical engineering in Urmia University, Urmia, Iran. His research interests are analog and digital integrated circuits and high-speed high-resolution data converters.

N. Mohabbatian

Neda Mohabbatian was born in Urmia, Iran in 1985. She received her BS degree from Urmia University, Urmia, Iran in 2007, MS degree from Urmia University, Urmia, Iran in 2011, both in electrical engineering. She is currently with Electrical Engineering group in Urumi Graduate Institue, Urmia, Iran. Email: [email protected]

Kh. Hadidi

Khayrollah Hadidi received his BS degree from Sharif University of Technology, Tehran, Iran, the MS degree from Polytechnic University, New York, and the PhD degree from University of California, Los Angeles, CA, USA, all in electrical engineering. His research interests are high-speed high-resolution data converter design, wideband integrated filter design, and nonlinearity analysis and improvement in analog circuits. He is currently with Electrical Engineering Department and Microelectronics Research Laboratory in Urmia University, Urmia, Iran. He holds 4 US, UK and German patents (issued), plus 12 Japanese patents (pending). Email: [email protected]