CMOS Implementation of a Novel High Speed 4:2 Compressor for Fast Arithmetic Circuits

References

• K. S. Sahoo, and C. Shekhar, “Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4:2 compressor,” Int. J. Electron., Vol. 95, no. 2, pp. 139–157, 2008.
   Web of Science ®Google Scholar
• A. M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 10, no. 1, pp. 20–29, Feb. 2002.
   Google Scholar
• M. Ghasemzadeh, N. Mohabbatian, A. Akbari, K. Hadidi, and A. Khoei. “A novel fast glitchless 7-3 counter with a new structure,” in 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Lublin, 2014, pp. 131–134.
   Google Scholar
• M. Ghasemzadeh, S. Mahdavi, A. Zokaei, and K. Hadidi. “A new ultra high speed 5-2 compressor with a new structure,” in 2016 MIXDES – 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 151–154.
   Google Scholar
• Z. Wang, G. A. Jullien, and W. C. Miller, “A new design technique for column compression multipliers,” IEEE Trans. Comput., Vol. 44, no. 8, pp. 962–970, Aug. 1995.
   Web of Science ®Google Scholar
• A. Weinberger, “4:2 Carry-save adder module,” IBM Tech. Discl. Bull., Vol. 23, no. 8, pp. 3811–3814, 1981.
   Google Scholar
• P. Aliparast, Z. D. Koozehkanani, and A. M. Khiavi, “A very high-speed CMOS 4-2 compressor using fully differential current-mode circuit techniques,” Analog Integr. Circ. Sig. Process, Vol. 66, pp. 235–243, 2011.
   Web of Science ®Google Scholar
• R. Marimuthu, M. Pradeepkumar, D. Bansal, S. Balamurugan, and P. S. Mallick. “Design of high speed and low power 15-4 compressor,” in 2013 International Conference on Communication and Signal Processing, Melmaruvathur, 2013, pp. 533–536.
   Google Scholar
• J. Tonfat, and R. Reis. “Low power 3–2 and 4–2 adder compressors implemented using ASTRAN,” 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), Playa del Carmen, pp. 1-4, 2012.
   Google Scholar
• C. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 51, no. 10, pp. 1985–1997, Oct. 2004.
   Web of Science ®Google Scholar
• K. Prasad, and K. K. Parhi. “Low-power 4-2 and 5-2 compressors,” in Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256), Pacific Grove, CA, USA, 2001, pp. 129–133.
   Google Scholar
• D. Radhakrishnan, and A. P. Preethy. “Low power CMOS pass logic 4-2 compressor for high-speed multiplication,” in Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), Lansing, MI, 2000, pp. 1296–1298.
   Google Scholar
• M. Ghasemzadeh, A. Akbari, A. Soltani, and K. Hadidi. “A new ultra high speed 7-2 compressor with a new structure,” in 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES), Torun, 2015, pp. 262–265.
   Google Scholar
• S. Veeramachaneni, K. M. Krishna, L. Avinash, S. R. Puppala, and M. B. Srinivas. “Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors,” in 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), Bangalore, 2007, pp. 324–329.
   Google Scholar
• S. C. Yuan, “4-2 compressor of fast booth multiplier for high-speed RISC processor,” Int. J. Electron., Vol. 94, no. 9, pp. 869–875, 2007.
   Web of Science ®Google Scholar
• M. Nagamatsu, S. Tanaka, J. Mori, T. Noguchi, and K. Hatanaka, “A 15ns 32×32-bit CMOS multiplier with an improved parallel structure,” IEEE J. Solid State Circ., Vol. 25, no. 2, pp. 494–497, 1990.
   Web of Science ®Google Scholar
• A. Fathi, S. Azizian, K. Hadidi, A. Khoei, and A. Chegeni. “CMOS implementation of a fast 4-2 compressor for parallel accumulations,” in 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, 2012, pp. 1476–1479.
   Google Scholar
• D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEE Proc. Circ. Devices Syst., Vol. 148, no. 1, pp. 19–24, Feb 2001.
   Google Scholar
• B. Razavi. Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001.
   Google Scholar
• N. Ohkubo, et al., “A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer,” in IEEE J. Solid State Circ., Vol. 30, no. 3, pp. 251–257, March 1995.
   Web of Science ®Google Scholar
• J. Mori, et al. “A 10 ns 54×54-bit parallel structured full array multiplier with 0.5 μm CMOS technology,” in Digest of Technical Papers., 1990 Symposium on VLSI Circuits, Honolulu, Hawaii, USA, 1990, pp. 125–126.
   Google Scholar
• H. Lin, R. C. Chang, and M. Chan. “Design of a novel radix-4 booth multiplier,” in the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Tainan, 2004, pp. 837–840.
   Google Scholar
• M. Nagamatsu, S. Tanaka, J. Mori, T. Noguchi, and K. Hatanaka. “A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure,” in 1989 Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, USA, 1989, pp. 10.3/1–10.3/4.
   Google Scholar
• M. Margala, and N. G. Durdle, “Low-power 4-2 compressor circuits,” Int. J. Electron., Vol. 85, no. 2, pp. 165–176, 1998.
   Web of Science ®Google Scholar
• D. Baran, M. Aktan, and V. G. Oklobdzija. “Energy efficient implementation of parallel CMOS multipliers with improved compressors,” in 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), Austin, TX, USA, 2010, pp. 147–152.
   Google Scholar
• R. Hussin, A. Y. M. Shakaff, N. Idris, Z. Sauli, R. C. Ismail, and A. Kamarudin. “An efficient Modified Booth multiplier architecture,” in 2008 International Conference on Electronic Design, Penang, 2008, pp. 1–4.
   Google Scholar
• A. Pishvaie, G. Jaberipur, and A. Jahanian, “High-performance CMOS (4:2) compressors,” Int. J. Electron., Vol. 101, no. 11, pp. 1511–1525, 2014.
   Web of Science ®Google Scholar
• P. Aliparast, Z. D. Koozehkanani, and F. Nazari, “An ultra high speed digital 4-2 compressor in 65-nm CMOS,” Int. J. Comp. Theory Eng., Vol. 5, no. 4, pp. 593–597, 2013.
   Google Scholar
• M. Ghasemzadeh, A. Akbari, K. Hadidi, and A. Khoei. “A novel fast glitchless 4-2 compressor with a new structure,” in 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Lublin, 2014, pp. 127–130.
   Google Scholar