High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation

Abstract

The major role of electronic devices is providing low power dissipation and high speed with compact area. The speed of electronic devices depends on arithmetic operations. Multiplication is the important arithmetic operation in many VLSI signal processing applications. Hence, a high-speed multiplier is needed to design any signal processing module. Many multipliers are surveyed in the literature. They are Array, Wallace tree, booth, Vedic and Compressor-based multiplier. The speed of these multipliers depends on partial product accumulation. The hybrid parallel adder-based multiplier is proposed to improve the speed of multiplication compared to the existing technique. In this technique the partial products of, two consecutive bits (multiplicands), are added simultaneously with the help of a hybrid adder (Hancarlson, Weinberger and Ling adder). The proposed architecture is synthesized and simulated using Xilinx ISE 12.1 with various FPGA boards. Synthesized report shows that the speed of proposed multiplier (Spartan 6 FPGA implementation) is improved when compared to an Array multiplier (22.14%), Wallace tree multiplier (20.41%), Multiplier using compressor (13.89%), Vedic Multiplier using CLA (13.03%), Vedic Multiplier using RCA (3.54%), Modified Booth multiplier (4.42%) and Vedic Multiplier using HCA with BEC (3.28%).

KEYWORDS:

• Area
• Delay
• FPGA
• Hybrid
• Multiplier
• Power
• Vedic
• VLSI
• Xilinx ISE 12.1

Additional information

Notes on contributors

V. Thamizharasan

V Thamizharasan is an assistant professor in the Department of Electronics and Communication Engineering at Erode Sengunthar Engineering College where he received his BE degree in electronics and communication engineering in 2008. He obtained ME degree in VLSI design from Kongu Engineering College, Erode (Anna University, Chennai) in 2010. He has 10 years of experience in the teaching field. He is a life member of ISTE. He has published about 6 papers in the reputed journals and in the national and international conferences. His research interests include low power VLSI, VLSI architecture and VLSI signal processing.

N. Kasthuri

N Kasthuri is professor in the Department of electronics and communication engineering, Kongu Engineering College, India. She received her BE degree in electronics and communication engineering from AC Tech Karaikudi and ME degree in applied electronics from the Bharathiyar University, Tamilnadu, India. She obtained her doctoral degree in information and communication engineering from Anna University, Chennai, Tamilnadu, India. She has two decades of teaching experience. She has published about 52 papers in the reputed journals and in the national and international conferences. Her research interests cover signal processing, speech signal processing and embedded systems. She received research grants from various funding agencies. She is a life member of ISTE. Email: [email protected]