FPGA Implementation of True Random Number Generator Architecture Using All Digital Phase-Locked Loop

Abstract

This study is a unique approach for the design and implementation of True Random Number Generator (TRNG) using ADPLL, on Field-Programmable Gate Array (FPGA) board Artrix-7 (XC7A35T-CPG236-1) and the simulation was done on Vivado v.2015.2 design suite. TRNG is solely based on the different seeds of entropy like Jitter, and metastability was produced from Ring Oscillator, Flip Flop (FF) and other primitives. In this paper, we have realized and implemented two architectures based on the use of ADPLL. TRNG with single ADPLL is represented as Novel design-1 (ND-1) and TRNG with two ADPLL as Novel design-2 (ND-2) cascading with other primitive like ring Oscillator combined with FF. Different from other approaches, this proposed TRNG architecture has higher speed, consumes less power in spite of employing 2 Look-Up-Tables (LUTs) and 1 slice block without compromising the overall throughput producing at 680.7 Mbps for ND-1 (Single ADPLL) and 676 Mbps for ND-2 (Two ADPLL). Comparing with other existing designs in the Field of TRNG and found out to have higher throughput and less power consumption, less complexity by employing a reduced FPGA hardware resource. Digital storage oscilloscope (DSO) is used to capture output waveform and FFT waveform for both ND-1 (single ADPLL) and ND-2 (two ADPLL). The randomness of the generated bitstream output of the design architecture is validated by passing the NIST SP 800-22 test which evidences that the proposed ADPLL-based TRNG can be better suited for different industrial applications such as security Network system, cybersecurity, Banking security, IIOT, IOT.

KEYWORDS:

• ADPLL
• DCO
• DSO-X3012A
• FPGA
• Ring Oscillator
• TRNG

Acknowledgements

The author conveys his deepest gratitude to Dr Manoj Kumar for his continuous support and advice while writing this article.

Additional information

Notes on contributors

Huirem Bharat Meitei

Huirem Bharat Meitei is now a PhD student at the National Institute of Technology, Manipur (India) and he earned his MTech degree in electronic and communication engineering from JNTU Kakinada, Andhra Pradesh. TRNG, IoT, FPGA design, and network security are among his research interests. He is also an associate member of The Institute of Engineers India (IEI). Corresponding author. Email: [email protected]

Manoj Kumar

Manoj Kumar is currently working as an assistant professor in the Department of Electronics and Communication Engineering, National Institute of Technology, Manipur. Having completed his BTech degree from NIT Calicut, and MTech degree from Indian Institute of Information Technology (IIIT), Allahabad, he started working as assistant professor in NIT Manipur and received his PhD degree from National Institute of Technology Manipur. He has published several research articles in national and international reputed journals and attended various conferences across India. His research area includes VLSI design, VLSI-DSP, digital electronics and communications. He has published over 25 scientific articles in international, national journals of repute and in several conferences. Email: [email protected]