Effect of NO(Si₃N₄/SiO₂) layers on the electrical properties of mfisfet using SBT (SrBi₂Ta₂O₉) materials

Abstract

We have developed the single ferroelectric field-effect-transistor technology using a ferroelectric SBT(SrBi₂Ta₂O₉) and NO(Si₃N₄/SiO₂) materials which were compatible with the standard Si CMOS process. The SBT/NO combined layer was used as a gate dielectric layer of MFISFET device. A small-sized MFISFET having 10/3um-width/length of gate was fabricated. The memory window of n-channel and p-channel MFISFET are all about 2.0 V. The threshold voltages of n-channel and p-channel MFISFET are about 1.8V and-2.1 V. The current difference between the I_ON(on current) and I_OFF(off current) for sensing margin is more than 100 times in I_D-V_G hysteresis curve. The retention property of MFISFET is examined by reading drain current after writing to the gate. The drain current as a function of retention time of MFISFET using NO layer remains almost the same value of its initial value over 10⁴ seconds at room temperature.

Key Words:

• Ferroelectric
• SBT
• MFISFET
• Si₃N₄
• Single Transistor