Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network

Abstract

Toward reconfigurable and noise-coexistence information processing system utilizing nanostructures, we study a threshold logic circuit and a double threshold function using a GaAs-based nanowire field-effect transistor (FET) network. A noise coexistence capability is based on a noise-assisted state transition in a threshold function in a threshold logic element. We fabricate a circuit reconfigurable between NAND and NOR functions. A hysteresis transfer characteristic with double threshold is realized in the GaAs nanowire by using a silicon nitride (SiN) as the gate insulator. We introduce a unique inverter design using the SiN-gate FET as a load to achieve the transfer characteristic with clockwise hysteresis, similar to a Schmitt trigger.

Implementation of a two-variable threshold logic with double threshold function using GaAs-based nanowire FETs.

Keywords:

• Word
• semiconductor nanowire network
• threshold logic
• hysteresis
• noise

Funding

This work was partly supported by Grant-in-Aid for Scientific Research on Innovative Areas ‘Molecular Architectonics: Orchestration of Single Molecules for Novel Functions’ [grant number #25110001] and ‘Implementation of information processing function on single-molecule-integrated networks and improvement of its reliability’ [grant number #25110013].