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Articles

Designing fault-tolerant network-on-chip router architecture

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Pages 1181-1192 | Received 19 Jul 2010, Accepted 27 Jul 2010, Published online: 06 Oct 2010

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Qianqi Le, Guowu Yang, William N. N. Hung, Xinpeng Zhang & Fuyou Fan. (2014) A multiobjective scatter search algorithm for fault-tolerant NoC mapping optimisation. International Journal of Electronics 101:8, pages 1056-1073.
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Rakotojaona Nambinina, Veit Wiese, Pascal Muoka, Daniel Onwuchekwa & Roman Obermaisser. (2023) Adaptive Time-Triggered Network-on-Chip Architecture: Enhancing Safety. Adaptive Time-Triggered Network-on-Chip Architecture: Enhancing Safety.
Zahra Shirmohammadi, Yassin Allivand, Fereshte Mozafari, Ahmad Patooghy, Mona Jalal & Sanaz Kazemi Abharian. (2022) ReNo: novel switch architecture for reliability improvement of NoCs. The Journal of Supercomputing 79:3, pages 2801-2818.
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Max Koenen, Nguyen Anh Vu Doan, Thomas Wild & Andreas Herkersdorf. (2021) Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs. Microprocessors and Microsystems 87, pages 104385.
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Hamed Zandevakili & Ali Mahani. (2020) Built-in self-repair structure for real-time fault recovery applications. Microelectronics Reliability 111, pages 113726.
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Tsotne Putkaradze, Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik & Gert Jervan. (2017) Fault-resilient NoC router with transparent resource allocation. Fault-resilient NoC router with transparent resource allocation.
Marco Balboni & Davide Bertozzi. (2017) Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels. Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.
M. Vijayaraj & K. Balamurugan. (2016) Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC. JSTS:Journal of Semiconductor Technology and Science 16:3, pages 359-366.
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Ashkan Eghbal, Pooria M. Yaghini, Nader Bagherzadeh & Misagh Khayambashi. (2015) Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip. IEEE Transactions on Computers 64:12, pages 3591-3604.
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Pooria M. Yaghini, Ashkan Eghbal & Nader Bagherzadeh. (2015) On the design of hybrid routing mechanism for mesh-based network-on-chip. Integration 50, pages 183-192.
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Misagh Khayambashi, Pooria M. Yaghini, Ashkan Eghbal & Nader Bagherzadeh. (2015) Analytical Reliability Analysis of 3D NoC under TSV Failure. ACM Journal on Emerging Technologies in Computing Systems 11:4, pages 1-16.
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Pooria M. Yaghini, Ashkan Eghbal, Siavash S. Yazdi & Nader Bagherzadeh. (2015) Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC. Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC.
Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi & Nader Bagherzadeh. (2014) TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip. TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip.
Abbas Banaiyanmofrad, Gustavo Girão & Nikil Dutt. (2014) NoC-based fault-tolerant cache design in chip multiprocessors. ACM Transactions on Embedded Computing Systems 13:3s, pages 1-26.
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Junxiu Liu, Jim Harkin, Yuhua Li & Liam Maguire. (2014) Online traffic-aware fault detection for networks-on-chip. Journal of Parallel and Distributed Computing 74:1, pages 1984-1993.
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Martin Radetzki, Chaochao Feng, Xueqian Zhao & Axel Jantsch. (2013) Methods for fault tolerance in networks-on-chip. ACM Computing Surveys 46:1, pages 1-38.
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