Designing fault-tolerant network-on-chip router architecture

References

• Acquaviva , A. and Bogliolo , A. 2003 . ‘A Bottom-Up Approach to On-Chip Signal Integrity’ . Lecture Notes in Computer Science , 2799 : 540 – 549 .
   Google Scholar
• Aidemark , J. , Vinter , J. , Folkesson , P. and Karlsson , J. ‘GOOFI: Generic Object-Oriented Fault Injection Tool’ . International Conference on Dependable Systems and Networks . pp. 83 – 88 .
   Google Scholar
• Ali , M. , Welzl , M. , Hessler , S. and Hellebrand , S. 2007 . ‘An Efficient Fault-Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip’ . International Journal of High Performance System Architecture , 1 : 113 – 123 .
   Google Scholar
• Avizienisv , A. , Laprie , J. C. , Randell , B. and Landwehr , C. ‘Basic Concepts and Taxonomy of Dependable and Secure Computing’ . IEEE Transactions on Dependable and Secure Computing . pp. 11 – 33 .
   Google Scholar
• Baumann , R. C. 2004 . ‘Soft Errors in Commercial Integrated Circuits’ . International Journal of High Speed Electronics and Systems , 14 : 299 – 309 .
   Google Scholar
• Dalirsani , A. , Hosseinabady , M. and Navabi , Z. ‘An Analytical Model for Reliability Evaluation of NoC Architectures’ . 13th IEEE International On-Line Testing Symposium . pp. 49 – 56 .
   Google Scholar
• Eghbal , A. , Yaghni , P. M. , Pedram , H. and Zarandi , H. R. ‘Fault Injection-Based Evaluation of a Synchronous NoC Router’ . 15th IEEE International On-Line Testing Symposium . pp. 212 – 214 .
   Google Scholar
• Eghbal , A. , Zarandi , H. R. and Yaghini , P. M. ‘Fault Tolerance Assessment of PIC Microcontroller Based on Fault Injection’ . 10th Latin American Test Workshop (LATW′09) . pp. 1 – 6 .
   Google Scholar
• Frantz , A. P. , Cassel , M. , Kastensmidt , F. L. , Cota , E. and Carro , L. ‘Crosstalk and SEU Aware Networks on Chips’ . IEEE Design and Test of Computers . pp. 340 – 350 .
   Google Scholar
• Frantz , A. P. , Kastensmidt , F. L. , Carro , L. and Cota , E. ‘Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk’ . IEEE International Test Conference . pp. 1 – 9 .
   Google Scholar
• Grecu , C. , Anghel , L. , Pande , P. P. , Ivanov , A. and Saleh , R. ‘Essential Fault-Tolerance Metrics for NoC Infrastructures’ . 13th IEEE International On-Line Testing Symposium . pp. 37 – 42 .
   Google Scholar
• Koibuchi , M. , Matsutani , H. , Amano , H. and Pinkston , T. M. ‘A Lightweight Fault-Tolerant Mechanism for Networks-on-Chip’ . Second ACM/IEEE International Symposium Networks-on-Chip . pp. 13 – 22 .
   Google Scholar
• Li , J. C.-M. , Lin , H.-M. and Wang , F.-M. ‘Column Parity and Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis’ . IEEE Transactions on Computers . pp. 402 – 414 .
   Google Scholar
• Marculescu , R. , Ogras , U. Y. , Peh , L.-S. , Jenger , N. E. and Hoskote , Y. 2009 . ‘Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives’ . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 28 : 3 – 21 .
   Web of Science ®Google Scholar
• Murali , S. , Theocharides , T. , Vijaykrishnan , N. , Irwin , M. J. , Benini , L. and De Micheli , G. ‘Analysis of Error Recovery Schemes for Networks on Chips’ . IEEE Design & Test of Computer . pp. 434 – 442 .
   Google Scholar
• Ogras , U. Y. , Hu , J. and Marculescu , R. ‘Key Research Problems in NoC Design: A Holistic Perspective’ . Proceedings of the 3rd International Conference on Hardware/Software Codesign and Systems Synthesis . pp. 60 – 74 .
   Google Scholar
• Pirretti , M. , Link , M. G. , Brooks , R. R. , Vijaykrishnan , N. , Kandemir , M. and Irwin , M. J. ‘Fault Tolerant Algorithms for Network-On-Chip Interconnect’ . Proceedings of the IEEE Computer Society Annual Symposium on VLSI . pp. 46 – 51 .
   Google Scholar
• Rantala , P. , Lehtonen , T. , Isoaho , J. and Plosila , J. ‘Fault-Tolerant Routing Approach for Reconfigurable Networks-on-Chip’ . International Symposium on System-on-Chip . pp. 1 – 4 .
   Google Scholar
• Zarandi , H. R. , Miremadi , S. G. and Ejlali , A. ‘Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models’ . Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems . pp. 485 – 492 .
   Google Scholar