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International Journal of Electronics Volume 97, 2010 - Issue 10: Evolutionary Synthesis of Network-on-Chip-Based Systems
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Articles

A high-performance, low-area reconfiguration controller for network-on-chip-based partial dynamically reconfigurable system-on-chip designs

Ling Wang Department of Computer Science, Harbin Institute of Technology, Harbin, 150001, ChinaCorrespondence[email protected]
,
Chunda Ding Department of Computer Science, Harbin Institute of Technology, Harbin, 150001, China
,
Dongxin Wen Department of Computer Science, Harbin Institute of Technology, Harbin, 150001, China
&
Yingtao Jiang Department of Computer and Electrical Engineering, University of Nevada, Las Vegas, USA
Pages 1207-1225 | Received 10 Nov 2009, Accepted 04 May 2010, Published online: 06 Oct 2010

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Abdessalem Ben Abdelali, Marwa Hannachi, Mohamed Nidhal Krifa, Hassan Rabah & Abdellatif Mtibaa. (2017) High-level design flow and environment for FPGA-based dynamic partial reconfiguration. International Journal of Electronics 104:8, pages 1254-1284.
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Articles from other publishers (1)

Gabriel Fornari & Valdivino Alexandre de Santiago Júnior. (2018) Dynamically Reconfigurable Systems: A Systematic Literature Review. Journal of Intelligent & Robotic Systems 95:3-4, pages 829-849.
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