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International Journal of Electronics Volume 101, 2014 - Issue 10
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Original Articles

Novel designs for fault tolerant reversible binary coded decimal adders

Ri-Gui ZhouCollege of Information Engineering, East China JiaoTong University, Nanchang, Jiangxi, P. R. China
,
Yan-Cheng LiCollege of Information Engineering, East China JiaoTong University, Nanchang, Jiangxi, P. R. ChinaCorrespondence[email protected]
&
Man-Qun ZhangCollege of Information Engineering, East China JiaoTong University, Nanchang, Jiangxi, P. R. China
Pages 1336-1356 | Received 11 Jun 2012, Accepted 04 Aug 2013, Published online: 05 Sep 2013

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Elbarbary Z. M. Salem, Azazi Haitham Z.Al-Gahtani Saad F.Mahmoud M. Elkholy. (2020) Open gate fault diagnosis and tolerant for voltage source inverter fed speed sensorless induction motor drive. International Journal of Electronics 107:11, pages 1754-1772.
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H. M. Gaur, A. K. Singh, A. Mohan & D. K. Pradhan. (2019) Computational analysis and comparison of reversible gates for design and test of logic circuits. International Journal of Electronics 106:11, pages 1679-1693.
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Asma Taheri Monfared & Majid Haghparast. (2017) Design of novel quantum/reversible ternary adder circuits. International Journal of Electronics Letters 5:2, pages 149-157.
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Ming-Cui Li & Ri-Gui Zhou. (2016) A novel reversible carry-selected adder with low latency. International Journal of Electronics 103:7, pages 1202-1215.
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Martín Vázquez & Elías Todorovich. (2016) FPGA-specific decimal sign-magnitude addition and subtraction. International Journal of Electronics 103:7, pages 1166-1185.
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Articles from other publishers (20)

Mojtaba Noorallahzadeh, Mohammad Mosleh & Kamalika Datta. (2023) A new design of parity-preserving reversible multipliers based on multiple-control toffoli synthesis targeting emerging quantum circuits. Frontiers of Computer Science 18:6.
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Seyed-Sajad Ahmadpour & Nima Jafari Navimipour. (2023) A new nano-design of 16-bit carry look-ahead adder based on quantum technology. Physica Scripta 98:12, pages 125108.
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Zahra Yazdanian-Amiri & Mojtaba Valinataj. (2023) High-speed binary coded decimal digit multipliers with multiple error detection. Integration 93, pages 102073.
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Mojtaba Noorallahzadeh, Mohammad Mosleh, Seyed‐Sajad Ahmadpour, Jayanta Pal & Bibhash Sen. (2023) A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 36:5.
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Mohammad Talebi, Mohammad Mosleh, Majid Haghparast & Mohsen Chekin. (2022) Effective scheme of parity-preserving-reversible floating-point divider. The European Physical Journal Plus 137:9.
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Meysam Rashno, Majid Haghparast & Mohammad Mosleh. (2021) Designing of Parity Preserving Reversible Vedic Multiplier. International Journal of Theoretical Physics 60:8, pages 3024-3040.
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F. Orts, G. Ortega, E.F. Combarro & E.M. Garzón. (2020) A review on reversible quantum adders. Journal of Network and Computer Applications 170, pages 102810.
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Mojtaba Noorallahzadeh & Mohammad Mosleh. (2019) Parity-preserving reversible flip-flops with low quantum cost in nanoscale. The Journal of Supercomputing 76:3, pages 2206-2238.
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Zahra Ariafar & Mohammad Mosleh. (2019) Effective Designs of Reversible Vedic Multiplier. International Journal of Theoretical Physics 58:8, pages 2556-2574.
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Ehsan PourAliAkbar & Mohammad Mosleh. (2019) An efficient design for reversible Wallace unsigned multiplier. Theoretical Computer Science 773, pages 43-52.
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Ghashmi H. Bin Talib, Aiman H. El-Maleh & Sadiq M. Sait. (2018) Design of Fault Tolerant Adders: A Review. Arabian Journal for Science and Engineering 43:12, pages 6667-6692.
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Horácio Neto & Mário Véstias. (2017) Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocessors and Microsystems 55, pages 91-99.
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Mojtaba Valinataj. (2017) Novel parity-preserving reversible logic array multipliers. The Journal of Supercomputing 73:11, pages 4843-4867.
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Slimani Ayyoub & Benslama Achour. (2017) Optimized 4-bit Quantum Reversible Arithmetic Logic Unit. International Journal of Theoretical Physics 56:8, pages 2686-2696.
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Xuemei Qi, Haihong Zhu, Fulong Chen, Junru Zhu & Ziyang Zhang. (2016) Novel Designs of Quantum Reversible Counters. International Journal of Theoretical Physics 55:11, pages 4987-4998.
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Trailokya Nath Sasamal, Anand Mohan & Ashutosh Kumar Singh. (2016) Design of parity preserving combinational circuits using reversible gate. Design of parity preserving combinational circuits using reversible gate.
Mojtaba Valinataj, Mahboobeh Mirshekar & Hamid Jazayeri. (2016) Novel low-cost and fault-tolerant reversible logic adders. Computers & Electrical Engineering 53, pages 56-72.
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Mojtaba Valinataj, Mahboobeh Mirshekar & Hamid Jazayeri. (2016) WITHDRAWN: Reversible logic adders: Novel low-cost fault-tolerant designs. Microprocessors and Microsystems.
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Ming-Cui Li & Ri-Gui Zhou. (2015) Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic. Journal of Circuits, Systems and Computers 24:06, pages 1550091.
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Rigui Zhou, Yancheng Li, Manqun Zhang & BenQiong Hu. (2014) Novel Design for Reversible Arithmetic Logic Unit. International Journal of Theoretical Physics 54:2, pages 630-644.
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