Citations (6)
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N. Agnes Shiny Rachel & G. Rajakumar. (2023) A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker. International Journal of Electronics 0:0, pages 1-21.
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Yogendra Gupta, Lava Bhargava, Ashish Sharma & M.S. Gaur. (2020) Hybrid buffers based coarse-grained power gated network on chip router microarchitecture. International Journal of Electronics 107:2, pages 272-287.
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S. C. Wagaj & S. C. Patil. (2019) Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits. International Journal of Electronics 106:7, pages 992-1007.
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Alak Majumder & Pritam Bhattacharjee. (2018) Variation aware intuitive clock gating to mitigate on-chip power supply noise. International Journal of Electronics 105:9, pages 1487-1500.
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Q. Tong & K. Choi. (2017) Activity correlation-based clustering clock-gating technique for digital filters. International Journal of Electronics 104:7, pages 1095-1106.
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Articles from other publishers (1)
Mohsen Imani, Shruti Patil & Tajana Rosing. (2016) Low power data-aware STT-RAM based hybrid cache architecture. Low power data-aware STT-RAM based hybrid cache architecture.