Performance centric design of subnetwork-based diagonal mesh NoC

ABSTRACT

Performance of NoC relies heavily on underlying interconnect network and related message forwarding technique. Here, Mesh is an obvious network choice by the designer due to its regular grid-based structure, making it easy to implement in chip surface. However, mesh suffers from degrading network performance issue in large-scale dimension due to the increasing hop count that leads to both congestion and link contention at the same time. Conventional topologies like Folded Torus, Butterfly-fat-tree (BFT) and recently proposed topologies like Flattened BFT, Sc-mesh and SD2D mesh topologies are mostly relying on express bypass links to mitigate this limitation in large-scale dimension. Proposed work presents a low latency oriented diagonally linked network that combines both 2 × 2 and a 1 × 1 diagonal links over the generic mesh connection to shorten the network diameter rendering chip designers more flexibility in regulating important performances centric design trade-offs such as packet delay, throughput and network energy while employing a low area overhead (~7%). Experimental results over 8 × 8 and 12 × 12 sized network show 8–11%, 18–66% and 60–66% lower packet delay while gain in throughput raises to 15–17%, 29–64% and 46–58% compared to 2-hop Dia-mesh (2x2 diagonal), Sc-mesh (1x1 diagonal) and conventional mesh topologies, respectively, under uniformly distributed traffic.

KEYWORDS:

• Network-on-Chip
• Topology
• Diagonally connected Mesh NoC
• Performance evaluation

Disclosure statement

No potential conflict of interest was reported by the authors.