An Advanced Method of Testing Memories Using a Vedic March Algorithm

Abstract

Nowadays, as the technology grows the size of the chip decreases, and RAM testing becomes more critical whose input and output ports are not controlled directly through the input or output pins of an IC. Because of the absence of controllability of RAM at the input or observing the output ports, testing is a tougher and more challenging effort. Multiple RAM testing is the main theme of the paper. Existing ways of testing RAMs for testing address data in random ways and missed corner cases, in the proposed system we come up with the new idea of testing RAMs using VMA (a Vedic March Algorithm). In the existing system using VMA tested a single RAM and by using a similar technique added multiple blocks of RAM and tested using VMA, for input generation of bits we used a BIST controller. we proved the 60% efficiency of the output is more comparable to the existing designs which standardize to improve march algorithms and observed a 10% decrease in the area compared to the existing systems. The proposed system uses a built-in self-test for generating a randomized cyclic address with the Vedic march algorithm which improves the level of testing of RAMs by randomizing reads and write flows to check and achieve higher efficiency. Simulation results are carried out by Synopsys VCS using Verilog HDL of reads and writes of different memories using March techniques.

KEYWORDS:

• BIST (Built-in self-test)
• RISC processor
• ROBDD
• Vedic march algorithm

Acknowledgements

The authors would like to thank Shri B H V S N Murthy, DS & Director, RCI and Prof Bheema Rao, Ex-HOD and Prof L. Anjaneyulu, HOD, ECE Dept. and also DRC members Prof CB Rama Rao, Prof J V Ramana Murthy NIT Warangal for their constant encouragement, valuable suggestions and support for carrying out this work as part of the PhD work.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

K.V.B.V. Rayudu

K V B V Rayudu graduated from the Institution of Electronics and Telecommunication Engineers (IETE), New Delhi in Dec 1990 and obtained MS Centre Imarat (RCI), DRDO, Hyderabad as a scientist in R&QA activities of missile systems. Contributed significantly to parts management, qualification, testing, failure analysis, reliability analysis and screening policy of electronic components and systems for aerospace applications. Planned and played key role for ISO 9001:2000 certification and Aerospace Quality Management System AS 9100:2009 certification to RCI, Hyderabad. His research interests include VLSI testing, VLSI fault simulation, modelling and diagnosis reliability analysis, failure analysis, quality management system certifications applications of ANN, GA and SVM for optimization, etc.

Jahagirdar

D R Jahagirdar received the BE degree in electronics engineering in 1990, from Govt. College of Engineering, Amravati University, Maharashtra, India. He received an MTech in microwave engineering in 1992, from the Indian Institute of Technology, Kharagpur, West Bengal, India. He was a research assistant at Sponsored Research and Industrial Consultancy at IIT, Kharagpur. Later, he joined the Antenna Products Division of Electronics Corporation of India Ltd, Hyderabad. He obtained a PhD in 1997 from the Department of Electronics and Computer Science, University of Southampton, UK. He received a scholarship from the Commonwealth Scholarship Commission UK to pursue the PhD. He joined Research Centre Imarat, DRDO, Hyderabad in May 2000. He won “Best Paper Award” at the University of Leeds, UK organized by the IEEE UKRI section. He received Prof S K Mitra Memorial Award for “Best Research Oriented Paper” from IETE in 2002. He received the Young Scientist Award at the IETE-IRSI International Radar Symposium in Bangalore in 2005. He also received a laboratory scientist of the year award in 2006. He is a fellow of IETE and a senior member of IEEE, Antennas and Propagation Society and Microwave Theory and Techniques Society. He is also a member of URSI. Recently he has been listed in Marquis ‘Who's Who in the World. His area of interest is microwave antennas and arrays for radars. Email: [email protected]

P Srihari Rao

Sriharirao Patri is working as an associate professor at NIT, Warangal Telangana, India in the Dept. of ECE. His research interests include RFIC design, VLSI testing, fault diagnosis analog/ digital IC design, DSP architecture, and analog LDOs. He has published 10 technical papers in international journals/presented in conferences. He has conducted various courses in the VLSI area and guided 5PhD students. Email: [email protected]