An Advanced Method of Testing Memories Using a Vedic March Algorithm

References

• J.-C. Lo, C. Metra, and F. Lombardi, “Guest editors’ introduction: special section on design and test of systems-on-chip (SoC),” IEEE Trans. Comput., Vol. 55, no. 2, pp. 97–8, Feb. 2006. DOI: 10.1109/TC.2006.26
   Web of Science ®Google Scholar
• J.-F. Frigon, A. M. Eltawil, E. Grayver, A. Tarighat, and H. Zou, “Design and implementation of a baseband WCDMA dual-antenna mobile terminal,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 54, no. 3, pp. 518–29, Mar. 2007. DOI: 10.1109/TCSI.2006.887620
   Web of Science ®Google Scholar
• D. Kim, et al., “An SoC with 1.3 Gtexels/s 3-D graphics full pipeline for consumer applications,” IEEE J. Solid-State Circuits, Vol. 41, no. 1, pp. 71–84, Jan. 2006. DOI: 10.1109/JSSC.2005.859330
   Web of Science ®Google Scholar
• A. Lodi, et al., “XiSystem: a XiRisc-based SoC with reconfigurable IO module,” IEEE J. Solid-State Circuits, Vol. 41, no. 1, pp. 85–96, Jan.2006. DOI: 10.1109/JSSC.2005.859319
   Web of Science ®Google Scholar
• Y. Zorian, and D. Gizopoulos, “Guest editors’ introduction: design for yield and reliability,” IEEE Des. Test. Comput., Vol. 21, no. 3, pp. 177–82, Mar. 2004. DOI: 10.1109/MDT.2004.12
   Web of Science ®Google Scholar
• F. J. Meyer, and N. Park, “Predicting defect-tolerant yield in the embedded core context,” IEEE Trans. Comput., Vol. 52, no. 11, pp. 1470–9, Nov. 2003. DOI: 10.1109/TC.2003.1244944
   Web of Science ®Google Scholar
• T. Koshy, and C. S. Arun, “Diagnostic data detection of faults in RAM’s using different march algorithms with BIST scheme,” in 2016 international Conference on Emerging Technological Trends (ICETT), Kollam, 2016.
   Google Scholar
• S. Banerjee, R. C. Dipanwita, and B. Bhargab. Bhattacharya, in proceedings of the 2005 IEEE International Workshop on Memory Technology, Desgin and Testing (MTDT’05).
   Google Scholar
• The national Roadmap for Semiconductors. 2000. Semiconductor Industry Association.
   Google Scholar
• E. Eric Dupont, M. Nicolaidis, and P. Rohr. Embedded Robustness IPs forTransient Error free ICs. IEEE Design & Test of Computers, 2002.
   Google Scholar
• E. Dupont, M. Nicolaidis, and P. Rohr, “Embedded robustness IPs for transient error free ICs,” IEEE Des. Test Comput., Vol. 19, no. 3, pp. 56–70, May–June, 2002.
   Web of Science ®Google Scholar
• J. van de Goor. Testing Semiconductor Memories: Theory and Practice. A.J.vandeGoor, 1998.
   Google Scholar
• A. J. Van De Goor, and I. Sehanstra. Address and data scrambling: causes and impact on memory tests. Christchurch: IEEE DELTA Workshop, January 2002.
   Google Scholar
• E. R. Manoj Arora, and E. Shipra Tripathi, “Comparative simulation of MBIST using march test algorithms,” Int. J. Scientific & Eng Res., Vol. 2, no. 12, December-2011.
   Google Scholar
• R. Dreschler, J. Shi, and G. Fey, “Synthesis of fully testable circuits from BDDs,” IEEE Trans. Comput-Aided Des Integrated Circuits and Syst., Vol. 23, no. 3, pp. 1–4, 2004. DOI: 10.1109/TCAD.2004.824981
   Web of Science ®Google Scholar
• M. Fujita, and A. Mishenko, “Efficient SAT-based ATPG techniques for all multiple stuck-at faults,” IEEE International Test Conference(ITC), 1–10, 2014.
   Google Scholar
• Yingke Gao, Diancheng Wu, Quanquan Li, Tiejun Zhang, and Chaohuan Hou. Design and implementation of transaction level processor based on uvm. In 2013 IEEE 10th International Conference on ASIC, 1–4, Oct 2013.
   Google Scholar
• S. Barua, “Computer-based multimedia system on “computer organization and design,” in 1997 IEEE International Conference on Systems, Man, and Cybernetics. Computational Cybernetics and Simulation, 1997, pp. 614–9.
   Google Scholar
• H. Thapliyal, N. Ranganathan, and S. Kotiyal, “Design of testable reversible sequential circuits,” IEEE Trans Very Large Scale Integration (VLSI) Syst., Vol. 21, no. 7, pp. 1201–9, July 2013. DOI: 10.1109/TVLSI.2012.2209688.
   Web of Science ®Google Scholar
• A. Yadav, and V. Bendre, “Design and Verification of 16 bit RISC Processor Using Vedic Mathematics,” in 2021 international Conference on Emerging Smart Computing and Informatics (ESCI), Pune, India, 2021, pp. 759–64, DOI: 10.1109/ESCI50559.2021.9396965.
   Google Scholar
• T. Shah, A. Matrosova, and V. Singh, “Test pattern generation to detect multiple faults in ROBDD based combinational circuits,” in 2017 ieee 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), Thessaloniki, Greece, 2017, pp. 211–2, DOI: 10.1109/IOLTS.2017.8046223.
   Google Scholar
• K. L. V. R. Kumari, M. A. Rani, and N. Balaji, “Fpga Implementation of Memory Design and Testing,” in 2017 IEEE 7th International Advance Computing Conference (IACC), 2017, pp. 552–5. DOI: 10.1109/IACC.2017.0119.
   Google Scholar
• K. Veera Bhoga Vasantha Rayudu, J. Jahagirdar, and P. Rao, “Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks,” Int J Reconfigurable and Embedded Syst. (IJRES), Vol. 9, no. 2, pp. 158∼168, July 2020. DOI: 10.11591/ijres.v9.i2.pp158-168. ISSN: 2089-4864.
   Google Scholar
• R. Sharma, V. K. Sehgal, N. Nitin, P. Bhasker, and I. Verma, “Design and Implementation of a 64-bit RISC Processor Using VHDL,” in 2009 11th international Conference on Computer Modelling and Simulation, Cambridge, UK, 2009, pp. 568–73, DOI: 10.1109/UKSIM.2009.30.
   Google Scholar