Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics

ABSTRACT

Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined impact’ of NBTI degradation along with the process, voltage and temperature (PVT) variations on SRAM metrics. These issues impact the performance of SRAM (Static Random Access Memory) cell in many ways but the two main dynamic metrics are critical read-stability and write-ability. The dynamic metrics can, in turn, be characterised by their static metrics, that determine the static noise margins (SNM) of SRAM. The dynamic metrics were analysed for symmetric and asymmetric NBTI degradation of two inverters of SRAM. NBTI degradations were incorporated on the pull-up transistors of SRAM cell. Furthermore, results of the correlated performance metrics are presented for varied data storage patterns in SRAM cell over its lifetime. This analysis aims to provide an insight into the effects of integrated PVT and NBTI degradation on SRAM cell performance, enabling robust designs and help designers at the early stage of design to mitigate system failure.

KEYWORDS:

• SRAM cell
• PVT
• NBTI degradation
• dynamic metrics
• static metrics

Acknowledgements

The authors would like to thank the Department of Electrical and Electronics Engineering, BITS Pilani – Dubai Campus, U.A.E. and the team of Cadence Academic Network for providing essential resources to perform simulations required for the work conducted in this paper. The authors are thankful for the support extended towards simulation resources from the Electrical Engineering Department of Shiv Nadar University, India.

Disclosure statement

No potential conflict of interest was reported by the author(s).