References
- Alimin, A. F. M., Radzi, A. A. M., Sazali, N. A. F., Hatta, S. F. W. M., Soin, N., & Hussain, H. (2017). Influence of design and process parameters of 32-nm advanced-process high-k p-MOSFETs on negative-bias temperature instability and study of defects. Journal of Electronic Materials, 46(10), 5942–5949. https://doi.org/https://doi.org/10.1007/s11664-017-5575-9
- Asenov, A. (2007). Simulation of statistical variability in nano MOSFETs. Digest of Technical Papers - Symposium on VLSI Technology, 1(2006), 86–87. https://doi.org/https://doi.org/10.1109/VLSIT.2007.4339737
- Bhavnagarwala, A. J., Tang, X., & Meindl, J. D. (2001). The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE Journal of Solid-State Circuits, 36(4), 658–665. https://doi.org/https://doi.org/10.1109/4.913744
- Chaudhari, S. P., Shaik, J. B., Singhal, S., & Goel, N. (2018, December 17-19). Correlation of dynamic and static metrics of SRAM cell under time-zero variability and after NBTI degradation. Proceedings - 2018 IEEE 4th international symposium on smart electronic systems, ISES 2018, 90–93. Hyderabad, India. https://doi.org/https://doi.org/10.1109/iSES.2018.00028
- Goel, N., Dubey, P., Kawa, J., & Mahapatra, S. (2015, April 19-23). Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages. IEEE international reliability physics symposium proceedings, 2015-May, CA51–CA57. Monterey, CA, USA. https://doi.org/https://doi.org/10.1109/IRPS.2015.7112783
- Goel, N., Joshi, K., Mukhopadhyay, S., Nanaware, N., & Mahapatra, S. (2014). A comprehensive modelling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs. Microelectronics Reliability, 54(3), 491–519. https://doi.org/https://doi.org/10.1016/j.microrel.2013.12.017
- Grasser, T., Kaczer, B., Goes, W., Th., A., Ph., H., & Nelhiebel, M. (2009). Understanding negative bias temperature instability in the context of hole trapping (Invited Paper). Microelectronic Engineering, 86(7–9), 1876–1882. https://doi.org/https://doi.org/10.1016/j.mee.2009.03.120
- Grossar, E., Stucchi, M., Maex, K., & Dehaene, W. (2006). Read stability and write-ability analysis of SRAM cells for nanometer technologies. IEEE Journal of Solid-State Circuits, 41(11), 2577–2588. https://doi.org/https://doi.org/10.1109/JSSC.2006.883344
- Guo, Z., Carlson, A., Pang, L., Duong, K. T., Liu, T. K., & Nikolic, B. (2009). Large-scale SRAM variability characterization in 45 nm CMOS. IEEE Journal of Solid-State Circuits, 44(11), 3174–3192. https://doi.org/https://doi.org/10.1109/JSSC.2006.883344
- Jiajing, W., Singhee, A., Rutenbar, R. A., Benton, H., & Calhoun, B. H. (2010). Two fast methods for estimating the minimum standby supply voltage for large SRAMs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(12), 1908–1920. https://doi.org/https://doi.org/10.1109/TCAD.2010.2061810
- Kerber, A., & Nigam, T. (2013, April 14-18). Challenges in the characterization and modeling of BTI induced variability in metal gate/High-k CMOS technologies. IEEE international reliability physics symposium proceedings, 2–7. Anaheim, CA, USA. https://doi.org/https://doi.org/10.1109/IRPS.2013.6531959
- Kerber, A., & Nigam, T. (2018). Bias temperature instability in scaled CMOS technologies: A circuit perspective. Microelectronics Reliability, 81, 31–40. https://doi.org/https://doi.org/10.1016/j.microrel.2017.12.006
- Kumar, A., Rabaey, J., & Ramchandran, K. (2009). SRAM supply voltage scaling: A reliability perspective. Proceedings of the 10th international symposium on quality electronic design, ISQED 2009, 782–787.San Jose, CA, USA. https://doi.org/https://doi.org/10.1109/ISQED.2009.4810392
- Mahapatra, S., Goel, N., Desai, S., Gupta, S., Jose, B., Mukhopadhyay, S., & Alam, M. A. (2013). A comparative study of different physics-based NBTI models. IEEE Transactions on Electron Devices, 60(3), 901–916. https://doi.org/https://doi.org/10.1109/TED.2013.2238237
- Mishra, S., Parihar, N., Anandkrishnan, R., Dabhi, C. K., Chauhan, Y. S., & Mahapatra, S. (2018). NBTI-related variability impact on 14-nm node FinFET SRAM performance and static power: Correlation to time zero fluctuations. IEEE Transactions on Electron Devices, 65(11), 4846–4853. https://doi.org/https://doi.org/10.1109/TED.2018.2869669
- Mukhopadhyay, S., Goel, N., & Mahapatra, S. (2016). A comparative study of NBTI and PBTI using different experimental techniques. IEEE Transactions on Electron Devices, 63(10), 4038–4045. https://doi.org/https://doi.org/10.1109/TED.2016.2599854
- Naphade, T., Verma, P., Goel, N., & Mahapatra, S. (2014, June 1-5). DC/AC BTI variability of SRAM circuits simulated using a physics-based compact model. 2014 IEEE international reliability physics symposium, Waikoloa, HI, USA. https://doi.org/https://doi.org/10.1109/IRPS.2014.6861119
- Parihar, N., Goel, N., Mukhopadhyay, S., & Mahapatra, S. (2018). BTI analysis tool—modelling of NBTI DC, AC stress and recovery time kinetics, nitrogen impact, and EOL estimation. IEEE Transactions on Electron Devices, 65(2), 392–403. https://doi.org/https://doi.org/10.1109/TED.2017.2780083
- Picardo, S. M., Shaik, J. B., Sahni, S., Goel, N., & Singhal, S. (2020). Analyzing the impact of NBTI and process variability on dynamic SRAM metrics under temperature variations. In: N. Goel, S. Hasan, & V. Kalaichelvi (Eds.), Modelling, simulation and intelligent computing. MoSICom 2020. lecture notes in electrical engineering (Vol. 659, pp. 608–616). Springer.
- Ruchi, & Dasgupta, S. (2017). 6T SRAM cell analysis for DRV and read stability. Journal of Semiconductors, 38(2), 025001. https://doi.org/https://doi.org/10.1088/1674-4926/38/2/025001
- Seevinck, E., List, F. J., & Lohstroh, J. (1987). Static-noise margin analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits, 22(5), 748–754. https://doi.org/https://doi.org/10.1109/JSSC.1987.1052809
- Shaik, J. B., Chaudhari, S. P., Singhal, S., & Goel, N. (2018, December 16-18). Analyzing impact of NBTI and time-zero variability on dynamic SRAM metrics. 15th IEEE India council international conference, Coimbotore, India.
- Shaik, J. B., Singhal, S., & Goel, N. (2020). Analysis of SRAM metrics for data dependent BTI degradation and process variability. Integration, the VLSI Journal, 72, 148–162. https://doi.org/https://doi.org/10.1016/j.vlsi.2020.01.006
- Singh, J., Mohanty, S. P., & Pradhan, D. K. (2013). Robust SRAM designs and analysis. Springer Publishing Company, Incorporated.
- Toh, S. O., Guo, Z., Liu, T. K., & Nikolic, B. (2011). Characterization of dynamic SRAM stability in 45 nm CMOS. IEEE Journal of Solid-state Circuits, 46(11), 2702–2712. https://doi.org/https://doi.org/10.1109/JSSC.2011.2164300
- Wang, X., Brown, A. R., Cheng, B., & Asenov, A. (2011, December 5-7). Statistical variability and reliability in nanoscale FinFETs. Technical digest - international electron devices meeting, IEDM, 103–106. Washington, DC, USA https://doi.org/https://doi.org/10.1109/IEDM.2011.6131494
- Ye, Y., Gummalla, S., Wang, C. C., Chakrabarti, C., & Cao, Y. (2010). Random variability modeling and its impact on scaled CMOS circuits. Journal of Computational Electronics, 9, 108–113. https://doi.org/https://doi.org/10.1007/s10825-010-0336-5
- Zhang, K., Bhattacharya, U., Chen, Z., Hamzaoglu, F., Murray, D., Vallepalli, N., Wang, Y., Zheng, B., & Bohr, M. (2006). A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE Journal of Solid-State Circuits, 41(1), 146–151. https://doi.org/https://doi.org/10.1109/JSSC.2005.859025