A Novel Double-Gate MOSFET Architecture as an Inverter

Abstract

In this work, a novel structure of a double-gate MOSFET is proposed and simulated. The CMOS inverter action in a single device realized by combining p-mode and n-mode MOS transistors is presented. The main advantage of the proposed device is fewer transistors for implementing sequential and combinational circuits. The significant reduction of the transistors, while designing a combinational circuit, will enhance the electronic industry with less power consumption. In our proposed device, a single substrate is used in comparison to the conventional CMOS inverter. The proposed device reduces short channel effects at lesser channel length. For L_g= 50nm, the proposed device, as an inverter, offers a unique VTC curve, SNM, V-curve along with sound values of performance parameters individually for p-mode and n-mode. A significant reduction in the junctions, wells and oxide regions can be seen from the proposed inverter design. Besides the performance of the device, the fabrication steps and the layout of the DGMOSFET-I are also presented in work.

KEYWORDS:

• Double-gate
• Inverter
• MOSFET
• Short channel effects
• TCAD

ACKNOWLEDGEMENTS

The authors would like to thank Mr. Amit Saini Cadre’s design system for their technical support. They also thank the Department of Electronics and Communication Engineering, Om Sterling Global University, for the lab support.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Author’s Contributions

Author’s have equally contributed to the work.

Additional information

Notes on contributors

Aakansha

Aakansha received the MTech degree from The North Cap University, Gurugram India, in VLSI design in 2013. Currently, she is pursuing a PhD degree in the Department of Electronics and Communication Engineering at Om Sterling Global University, Hisar, Haryana, India. Her areas of interest are CMOS, device design, and their applications.

Manoj Kumar

Manoj Kumar received the PhD degree from I K Gujaral Punjab Technical University, Jalandhar Punjab, India, in 2019 with a dissertation on the effect of channel materials on electrical characteristics of nano FETs. Currently, he is with the Department of Electronics and Communication Engineering at Om Sterling Global University, Hisar, Haryana, India. His research interests include CMOS reliability, microelectronics, simulation and modeling of nanotube, nanowires, nanorods, nanostructures, and nano devices. Email: [email protected]