Novel PZT Capacitor Technology for High Density FRAM Device with 0.18 μm D/R

Abstract

Novel capacitor technologies for high density FRAM device with 0.18 μm D/R (design-rule) have been researched and developed. In order to realize the high-density FRAM device with 0.18 μm D/R, the PZT film was modified by changing Zr/Ti composition and by using PTO seeding layer. Therefore, the crystallization temperature of the PZT film could be successfully lowered to 550°C. The remnant polarization of PTO-used 100 nm thick PZT capacitors measured at 2.7 V was approximately 24 μC/cm ² , that is 30% higher than that of the PTO-unused PZT capacitors. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Furthermore, by lowering the PZT crystallization temperature and by applying robust TiAlN oxidation barrier, low (300 Ω/contact) and stable contact resistance in a very small size of BC could be obtained. Finally, we successfully developed a capacitor stack height of 270 nm. The capacitor size was 0.26 × 0.44 μm² and remnant polarization measured at 2.7 V was approximately 11 μC/cm².

Keywords:

• FRAM
• PZT
• capacitor
• PbTiO₃ (PTO)
• seeding layer