Designing fault-tolerant network-on-chip router architecture

Abstract

In this article, a fault-tolerant network-on-chip (NoC) router architecture is introduced. This article reports a comprehensive fault study of a NoC router through a simulation-based method. The evaluation of single-event transient (SET), crosstalk and single-event upset (SEU) fault injections shows that up to 53% of the injected faults cause a system failure. About 45% of them are replaced by new values before turning into errors and almost 1% of them are treated as latent errors. According to the experimental results, routing units and switch components are known as the two most unstable elements with regard to transient injected faults, with failure rates of 60% and 55%, respectively. Moreover, the effects of SETs are greater in all components. The SEUs also have a tangible effect on the functionality of the routing unit. Using column parity row selection method as an SEU-tolerant one in the routing unit and an innovative SET-crosstalk-tolerant technique in the switch components has mitigated the total failure rate down to 38%. The synthesis of fault-tolerant architecture requires almost 22% more area than the non-tolerant architecture. The proposed fault-tolerant method consumes almost 27% less dynamic power than a Hamming triple modular redundancy method.

Keywords:

• network-on-chip router
• fault evaluation
• SET
• SEU
• crosstalk
• fault-injection
• fault-tolerant technique