Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

ABSTRACT

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.

KEYWORDS:

• Fully Depleted Silicon-On-Insulator (FDSOI)
• underlap structure
• two-dimensional (2-D) analytical model
• surface potential
• short-channel effects

Acknowledgment

This work is supported by Government of India under Technical Education Quality Improvement Program – Phase II (TEQIP-II), via grant no. F.No.16-6/2013-TS.VII (Pt).

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

This work is supported by Government of India under Technical Education Quality Improvement Program – Phase II (TEQIP-II), via grant no. F.No.16-6/2013-TS.VII (Pt).